AD8191 Analog Devices, AD8191 Datasheet - Page 21

• Manufacturer Part Number: AD8191
• Description: 4:1 DVI/HDMI Switch with Equalization Preliminary Data Sheet (Rev. PrJ, 8/2006)
• Manufacturer: Analog Devices

Preliminary Technical Data
PCB LAYOUT GUIDELINES
The AD8191 is used to switch two distinctly different types of
signals, both of which are required for HDMI and DVI video.
These signal groups require different treatment when laying out
a PC board.
The first group of signals carries the audiovisual data. HDMI/DVI
video signals are differential, unidirectional, and high speed (up
to 1.65 Gbps). The channels that carry the video data must be
controlled impedance, terminated at the receiver, and capable of
operating up to at least 1.65 Gbps. It is especially important to
note that the differential traces that carry the TMDS signals
should be designed with a controlled differential impedance of
100 Ω. The AD8191 provides single-ended 50 Ω terminations
on-chip for both its inputs and outputs, and both the input and
output terminations can be enabled or disabled through the
serial interface. Transmitter termination is not fully specified by
the HDMI standard but its inclusion improves the overall system
signal integrity.
The audiovisual (AV) data carried on these high speed channels
is encoded by a technique called transmission minimized differ-
ential signaling (TMDS) and in the case of HDMI, is also encrypted
according to the high bandwidth digital copy protection (HDCP)
standard.
The second group of signals consists of low speed auxiliary
control signals used for communication between a source and a
sink. Depending upon the application, these signals can include
the DDC bus (this is an I
and HDCP encryption keys between the source and the sink),
the consumer electronics control (CEC) line, and the hot plug
detect (HPD) line. These auxiliary signals are bidirectional, low
speed, and transferred over a single-ended transmission line
that does not need to have controlled impedance. The primary
concern with laying out the auxiliary lines is ensuring that they
conform to the I
capacitive loading.
TMDS SIGNALS
In the HDMI/DVI standard, four differential pairs carry the
TMDS signals. In DVI, three of these pairs are dedicated to
carrying RGB video and sync data. For HDMI, audio data is
also interleaved with the video data; the DVI standard does
not incorporate audio information. The fourth high speed
differential pair is used for the AV data-word clock, and runs
at one-tenth the speed of the TMDS data channels.
The four high speed channels of the AD8191 are identical.
No concession was made to lower the bandwidth of the fourth
channel for the pixel clock, so any channel can be used for any
TMDS signal. The user chooses which signal is routed over
which channel. Additionally, the TMDS channels are symmetrical;
therefore, the p and n of a given differential pair are inter-
changeable, provided the inversion is consistent across all inputs
2
C bus standard and do not have excessive
2
C bus used to send EDID information
Rev. PrJ | Page 21 of 29
and outputs of the AD8191. However, the routing between
inputs and outputs through the AD8191 is fixed. For example,
Output Channel 0 always switches between Input A0 and
Input B0, and so forth.
The AD8191 buffers the TMDS signals and the input traces can
be considered electrically independent of the output traces. In
most applications, the quality of the signal on the input TMDS
traces are more sensitive to the PCB layout. Regardless of the
data being carried on a specific TMDS channel, or whether the
TMDS line is at the input or the output of the AD8191, all four
high speed signals should be routed on a PCB in accordance
with the same RF layout guidelines.
LAYOUT FOR THE TMDS SIGNALS
The TMDS differential pairs can either be microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 Ω. The
characteristic impedance of a differential pair is a function of
several variables including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PC board binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path, therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. Additionally, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together in order to establish the required 100 Ω
differential impedance. Enough space should be left between
the differential pairs of a given group so that the n of one pair
does not couple to the p of another pair. For example, one tech-
nique is to make the interpair distance 4 to 10 times wider than
the intrapair spacing.
Any group of four TMDS channels (Input A, Input B, or the
output) should have closely matched trace lengths in order to
minimize interpair skew. Severe interpair skew can cause the
data on the four different channels of a group to arrive out of
alignment with one another. A good practice is to match the
trace lengths for a given group of four channels to within
0.05 inches on FR4 material.
AD8191