LM3S1165 Luminary Micro, Inc, LM3S1165 Datasheet - Page 274

• Manufacturer Part Number: LM3S1165
• Description: Lm3s1165 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Analog-to-Digital Converter (ADC)
12.3
12.3.1
12.3.2
12.4
Table 12-3. ADC Register Map
274
Offset
0x000
Name
ADCACTSS
Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and using a supported crystal
frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the
ADC module.
Module Initialization
Initialization of the ADC module is a simple process with very few steps. The main steps include
enabling the clock to the ADC and reconfiguring the Sample Sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1.
2.
Sample Sequencer Configuration
Configuration of the Sample Sequencers is slightly more complex than the module initialization
since each sample sequence is completely programmable.
The configuration for each Sample Sequencer should be as follows:
1.
2.
3.
4.
5.
6.
Register Map
Table 12-3 on page 274 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the ADC base address of 0x4003.8000.
Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC0 register (see page 98).
If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample
Sequencer 3 as the lowest priority.
Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in
the ADCACTSS register. Programming of the Sample Sequencers is allowed without having
them enabled. Disabling the Sequencer during programming prevents erroneous execution if
a trigger event were to occur during the configuration process.
Configure the trigger event for the Sample Sequencer in the ADCEMUX register.
For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the
ADCACTSS register.
Type
R/W
0x0000.0000
Reset
Preliminary
Description
ADC Active Sample Sequencer
July 26, 2008
page
See
276