LM3S1165 Luminary Micro, Inc, LM3S1165 Datasheet - Page 48

• Manufacturer Part Number: LM3S1165
• Description: Lm3s1165 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Interrupts
48
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Exception Type
Bus Fault
Usage Fault
-
SVCall
Debug Monitor
-
PendSV
SysTick
Interrupts
Vector Number
0-15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Vector
Number
16 and
above
7-10
12
13
14
15
11
5
6
Interrupt Number (Bit in
Interrupt Registers)
Priority
settable
settable
settable
settable
settable
settable
settable
-
-
10
11
12
13
14
15
16
17
18
19
20
0
1
2
3
4
5
6
7
8
9
-
a
Preliminary
Description
Pre-fetch fault, memory access fault, and other address/memory related
faults. This is synchronous when precise and asynchronous when
imprecise.
You can enable or disable this fault.
Usage fault, such as undefined instruction executed or illegal state
transition attempt. This is synchronous.
Reserved.
System service call with SVC instruction. This is synchronous.
Debug monitor (when not halting). This is synchronous, but only active
when enabled. It does not activate if lower priority than the current
activation.
Reserved.
Pendable request for system service. This is asynchronous and only
pended by software.
System tick timer has fired. This is asynchronous.
Asserted from outside the ARM Cortex-M3 core and fed through the
NVIC (prioritized). These are all asynchronous. Table 4-2 on page 48
lists the interrupts on the LM3S1165 controller.
Description
Processor exceptions
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
GPIO Port E
UART0
UART1
SSI0
I2C0
PWM Fault
PWM Generator 0
PWM Generator 1
PWM Generator 2
Reserved
ADC Sequence 0
ADC Sequence 1
ADC Sequence 2
ADC Sequence 3
Watchdog timer
Timer0 A
Timer0 B
July 26, 2008