LM3S1512 Luminary Micro, Inc, LM3S1512 Datasheet - Page 27
LM3S1512
Manufacturer Part Number
LM3S1512
Description
Lm3s1512 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1512.pdf
(508 pages)
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- Current page: 27 of 508
- Download datasheet (6Mb)
July 25, 2008
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GPIOs
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Power
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Flexible Reset Sources
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The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz PhA/PhB/IDX for a 50-MHz system)
Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature
error detection
15-58 GPIOs, depending on configuration
5-V-tolerant input/outputs
Programmable interrupt generation as either edge-triggered or level-sensitive
Low interrupt latency; as low as 6 cycles and never more than 12 cycles
Bit masking in both read and write operations through address lines
Can initiate an ADC sample sequence
Pins configured as digital inputs are Schmitt-triggered.
Programmable control for GPIO pad configuration:
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On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
Low-power options on controller: Sleep and Deep-sleep modes
Low-power options for peripherals: software controls shutdown of individual peripherals
User-enabled LDO unregulated voltage detection and automatic reset
3.3-V supply brown-out detection and reporting via interrupt or reset
Power-on reset (POR)
Reset pin assertion
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
configured with an 18-mA pad drive for high-current applications
Slew rate control for the 8-mA drive
Open drain enables
Digital input enables
Preliminary
LM3S1512 Microcontroller
27
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