LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 157
LM3S102
Manufacturer Part Number
LM3S102
Description
Lm3s102 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S102.pdf
(330 pages)
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July 6, 2006
Reset
Reset
Type
Type
GPTM Raw Interrupt Status (GPTMRIS)
Offset 0x01C
31:11
RO
RO
31
15
0
0
7:4
Bit
10
9
8
3
2
1
0
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
RO
RO
30
14
0
0
TBTORIS
TATORIS
reserved
CBMRIS
reserved
CAMRIS
CBERIS
RTCRIS
CAERIS
Name
reserved
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
CBERIS
RO
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
0
0
CBMRIS TBTORIS
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
Reserved bits return an indeterminate value, and should never
be changed.
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RTCRIS CAERIS
RO
RO
19
0
3
0
LM3S102 Data Sheet
RO
RO
18
0
2
0
CAMRIS TATORIS
RO
RO
17
0
1
0
RO
RO
16
0
0
0
157
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