LM3S8933 Luminary Micro, Inc, LM3S8933 Datasheet - Page 483

• Manufacturer Part Number: LM3S8933
• Description: Lm3s8933 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Ethernet MAC Timer Support (MACTS)
Base 0x4004.8000
Offset 0x03C
Type R/W, reset 0x0000.0000
17.6
July 25, 2008
Bit/Field
31:1
0
RO
RO
31
15
0
0
Register 16: Ethernet MAC Timer Support (MACTS), offset 0x03C
This register enables software to enable timer support on the transmission and reception of frames.
This register is only applicable for devices that have 1588 hardware support; for all others, a read
returns 0s.
MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers. All addresses given are
absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register
Descriptions” on page 465.
RO
RO
30
14
0
0
reserved
RO
RO
29
13
0
0
Name
TSEN
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
Reset
0x0
0x0
RO
RO
25
0
9
0
Preliminary
reserved
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Time Stamp Enable
When set, the TSEN bit multiplexes the TX and RX interrupts to the CCP
inputs of General-Purpose Timer 3.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S8933 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
0
1
0
TSEN
R/W
RO
16
0
0
0
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