MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet - Page 14

• Manufacturer Part Number: MT18VDDF6472G-202
• Description: 184-PIN REGISTERED DDR SDRAM DIMM
• Manufacturer: Micron

*AC timing values for -335 FBGA DDR SDRAM device.
64 Meg x72 184 Pin Registered DDR SDRAM DIMM
DDF18C64x72G_A.p65 – Pub. 02/02
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1–5, 12–15, 29; notes appear following parameter tables)
(0°C
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data Hold Skew Factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window (DVW)
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to V
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
T
A
+70°C; V
DD
Q = +2.5V ±0.2V, V
DD
CL = 2.5
CL = 2
DD
= +2.5V ±0.2V)
184-PIN REGISTERED DDR SDRAM DIMM
SYMBOL MIN
t
t
t
CK (2.5)
t
t
DQSCK
t
t
WPRES
t
t
t
t
t
t
t
t
t
CK (2)
DQSH
DQSQ
t
WPRE
WPST
t
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
t
t
XSNR
XSRD
MRD
t
RPRE
RPST
REFC
t
t
WTR
t
t
t
t
QHS
REFI
t
t
t
DSH
t
t
t
RAS
RAP
RCD
RRD
VTD
t
DSS
t
t
RFC
t
QH
WR
DH
na
AC
CH
DS
HP
HZ
IH
IH
IH
RC
CL
LZ
IS
RP
F
F
S
S
14
t
CH,
-
-0.75
-0.60
-0.70
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
t
0.25
200
t
t
7.5
0.2
0.2
.75
.75
.80
.80
QHS
0.9
0.4
0.4
12
42
18
60
72
18
18
12
15
75
HP
QH -
6
0
1
0
t
CL
-335
t
DQSQ
70,000
MAX
+0.75
+0.60
+0.75
0.50*
0.55
0.55
.35*
1.25
70.3
1.1
0.6
0.6
7.8
13
13
t
7.5/10
CH,
-
-0.75
-0.75
-0.75
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN
t
0.45
0.45
1.75
0.35
0.35
0.75
t
0.25
200
t
7.5
0.5
0.5
0.2
0.2
.90
.90
QHS
0.9
0.4
0.4
QH -
15
40
20
65
75
20
20
15
15
75
-26A/-265
HP
1
1
0
1
0
t
CL
t
DQSQ
120,000
MAX
+0.75
+0.75
+0.75
0.55
0.55
1.25
0.75
70.3
0.5
1.1
0.6
0.6
7.8
13
13
t
CH,
-
MIN
t
0.45
0.45
0.35
0.35
0.75
t
0.25
-0.8
-0.8
-0.8
200
0.2
0.2
1.1
1.1
1.1
1.1
t
0.9
0.4
0.4
QH -
0.6
0.6
QHS
10
16
40
20
70
80
20
20
15
15
80
HP
8
2
0
1
0
t
CL
-202
t
512MB (x72)
DQSQ
120,000
MAX
+0.8
0.55
0.55
+0.8
1.25
+0.8
70.3
1.1
0.6
0.6
7.8
0.6
13
13
1
PRELIMINARY
©2002, Micron Technology, Inc.
UNITS NOTES
t
t
t
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
CK
CK
ns
ns
CK
CK
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
40, 47
40, 47
23, 27
23, 27
16, 37
22, 23
18, 19
22, 23
16,38
26
26
27
30
12
12
12
12
31
41
45
37
17
22
21
21