MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet - Page 20

• Manufacturer Part Number: MT18VDDF6472G-202
• Description: 184-PIN REGISTERED DDR SDRAM DIMM
• Manufacturer: Micron

PLL CLOCK DRIVER TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
(Note: 1) (Specifications for the PLL component used on the module.)
NOTE: 1. The timing specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered
64 Meg x72 184 Pin Registered DDR SDRAM DIMM
DDF18C64x72G_A.p65 – Pub. 02/02
PARAMETER
Clock frequency
Input clock duty cycle
Stabilization time
Low-to high level
propagation delay time
High-to low level
propagation delay time
Output enable time
Output disable time
Jitter (peak-to-peak)
Jitter (cycle-to-cycle)
Phase error
Output skew
Pulse skew
Duty cycle
Output rise and fall times
(20% - 80%)
2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal.
DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed
information on this part has been shown at the JEDEC JC-40 Committee. Please contact Micron Technology's Module
Applications Team if further information on the specific register model is required.
1
SYMBOL
t
t
skew(o)
t
t
(phase
(jitter)
(jitter)
error)
t
t
t
t
t
PLH
PHL
t
r,
f
dis
dis
en
C
t
f
CK mode/CK to any output
CK mode/CK to any output
CK mode/G to any Y output
CK mode/G to any Y output
66 MHz
100/125/133/167 MHz
66 MHz
100/125/133/167 MHz
Terminated with 120 ohm/16pF
Terminated with 120 ohm/16pF
Terminated with 120 ohm/16pF
66 MHz to 100 MHz
101 MHz to 167 MHz
Load = 120 ohm/16pF
184-PIN REGISTERED DDR SDRAM DIMM
TEST CONDITIONS
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
49.5%
MIN
40%
49%
-150
650
1.5
1.5
66
NOM
512MB (x72)
800
3.5
3.5
3
3
PRELIMINARY
50.5%
MAX UNITS
©2002, Micron Technology, Inc.
60%
51%
167
120
110
150
100
100
950
0.1
75
65
6
6
MHz
ms
ns
ns
ns
ns
ps
ps
ns
ns
ns
ps