MT18VDDT6472 Micron, MT18VDDT6472 Datasheet - Page 3

• Manufacturer Part Number: MT18VDDT6472
• Description: 200-Pin DDR SDRAM SODIMMs (x72)
• Manufacturer: Micron

PIN DESCRIPTIONS
32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
WE#, CAS#, RAS#
CK1#, CK2, CK2#
A0-A11
CK0, CK0#, CK1,
A0-A12
DQS0-DQS17
CKE0, CKE1
DQ0-DQ63
SYMBOL
BA0, BA1
SA0-SA2
CB0-CB7
S0#, S1#
SDA
V
V
SCL
REF
DD
(256MB)
(512MB)
Input/Output
Input/Output
Input/Output
Input/Output
Supply
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Command Inputs: WE#, RAS#, and CAS# (along with S0#, S1#)
define the command being entered.
Clocks: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and DQS)
is referenced to the crossings of CK and CK#.
Clock Enables: CKE0 and CKE1 activate (HIGH) and deactivate (LOW)
internal clock signals, and device input buffers and output drivers.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE0 and CKE1 are synchronous for
all functions except for disabling outputs, which is achieved asyn-
chronously. CKE0 and CKE1 must be maintained HIGH throughout
read and write accesses. Input buffers (excluding CK0, CK0# and CKE)
are disabled during POWER-DOWN. Input buffers (excluding CKE0
and CKE1) are disabled during SELF REFRESH. CKE0 and CKE1 are
SSTL_2 inputs but will detect an LVCMOS LOW level after V
applied.
Chip Select: S0#, S1# enable (registered LOW) and disable (registered
HIGH) the command decoder. All commands are masked when S0#,
S1# are registered HIGH. S0#, S1# provide module bank selection.
S0#, S1# are considered part of the command code.
Bank Addresses: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE or PRECHARGE command is being applied.
Address Inputs: A0-A11/A12 are sampled during the
ACTIVE command (row-address A0-A11/A12) and READ/WRITE
command (column-address A0-A9, with A10 defining auto precharge)
to select one location out of the memory array in the respective
device device bank. A10 is sampled during a PRECHARGE command
to determine whether the PRECHARGE applies to one device bank
(A10 LOW) or all device banks (A10 HIGH). The address inputs also
provide the op-code during a MODE REGISTER SET command.
SSTL_2 reference voltage.
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
Data I/Os: Check bits.
Data Strobes: Output with read data, input with write data. Edge-
aligned with read data, centered in write data. Used to capture
write data.
Data I/Os: Data bus.
Serial Presence-Detect Data: SDA is a bidirectional pinused to
transfer addresses and data into and out of the presence-detect
portion of the module.
Power Supply: +2.5V +0.2V.
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-pin DDR SDRAM DIMMs
DESCRIPTION
256MB, 512MB (ECC x72)
©2002, Micron Technology, Inc.
DD
is