MT18VDDT6472 Micron, MT18VDDT6472 Datasheet - Page 9

• Manufacturer Part Number: MT18VDDT6472
• Description: 200-Pin DDR SDRAM SODIMMs (x72)
• Manufacturer: Micron

32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
EXTENDED MODE REGISTER
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC#. These functions are controlled via the bits
shown in the Extended Mode Register Definition Diagram.
The extended mode register is programmed via the LOAD
MODE REGISTER command to the mode register (with
BA0 = 1 and BA1 = 0) and will retain the stored information
until it is programmed again or the device loses power.
The enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode register
(BA0/BA1 both LOW) to reset the DLL.
device banks are idle and no bursts are in progress, and
the controller must wait the specified time before initiat-
ing any subsequent operation. Violating either of these
requirements could result in unspecified operation.
Output Drive Strength
fied to be SSTL2, Class II.
option, refer to 128Mb and 256Mb DDR SDRAM data
sheets.
DLL Enable/Disable
enable is required during power-up initialization and
upon returning to normal operation after having dis-
abled the DLL for the purpose of debug or evaluation.
(When the device exits self refresh mode, the DLL is
enabled automatically.) Any time the DLL is enabled, 200
clock cycles must occur before a READ command can be
issued.
The extended mode register controls functions beyond
The extended mode register must be loaded when all
The normal full drive strength for all outputs are speci-
For detailed information on output drive strength
The DLL must be enabled for normal operation. DLL
9
512MB Module
256MB Module
Extended Mode Register Definition
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-pin DDR SDRAM DIMMs
NOTE: 1. E13 and E12 (256MB module), or E14 and E13 (512MB Module)
E12
0
–
256MB, 512MB (ECC x72)
E11
1 1
14
BA1 BA0
0
–
2. The QFC# option is not supported.
0 1
E10
13
1 1
0
–
BA1 BA0
13
(BA0 and BA1) must be “1, 0” to select the Extended
Mode Register (vs. the base Mode Register).
0 1
12
E9
A12
0
–
12
11
E8
A11
0
–
11
A11
E7
10
0
–
A10
10
Diagram
A10
Operating Mode
E6 E5
0
–
9
A9
9
A9
0
–
8
Operating Mode
A8
8
A8
E4
0
–
7
A7 A6 A5 A4 A3
7
A7 A6 A5 A4 A3
E3
0
–
6
6
5
E2,
5
Valid
4
E1,
4
–
E0
3
3
QFC#
QFC
2
E2
2
A2 A1 A0
0
–
©2002, Micron Technology, Inc.
A2 A1 A0
2
DS
Operating Mode
Reserved
Reserved
DS
1
1
E1
0
1
DLL
DLL
1
0
0
E0
0
1
QFC# Function
Drive Strength
Reserved
Extended Mode
Register (Ex)
Disabled
Extended Mode
Register (Ex)
Address Bus
Address Bus
Reduced
Normal
Disable
Enable
DLL