MT18VDDT6472 Micron, MT18VDDT6472 Datasheet - Page 7

• Manufacturer Part Number: MT18VDDT6472
• Description: 200-Pin DDR SDRAM SODIMMs (x72)
• Manufacturer: Micron

32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
eration or incompatibility with future versions may re-
sult.
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-An when the burst length is set to two, by A2-Ai when
the burst length is set to four and by A3-Ai when the burst
length is set to eight (where Ai is the most significant
column address bit for a given configuration). The re-
512MB Module
256MB Module
Reserved states should not be used, as unknown op-
When a READ or WRITE command is issued, a block of
* M13 and M12 (BA0 and BA1)
* M14 and M13 (BA0 and BA1)
must be “0, 0” to select the
must be “0, 0” to select the
Mode Register Definition
base mode register (vs. the
base mode register (vs. the
extended mode register).
extended mode register).
0*
14
BA1
0*
0*
13
13
BA1
BA0
0*
12
12
A12 A11
BA0
Operating Mode
11
A11
11
Operating Mode
10
10
A10
A10
M12 M11
0
0
-
Diagram
9
9
A9
A9
0
0
-
8
8
A8
A8
M10
0
0
-
7
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
M9
M6
0
0
CAS Latency BT
-
CAS Latency BT
0
0
0
0
1
1
1
1
6
6
M8 M7
M5
0
1
-
0
0
1
1
0
0
1
1
5
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
4
M3
M6-M0
0
1
Valid
Valid
3
3
-
Burst Length
Burst Length
M2
2
2
0
0
0
0
1
1
1
1
A2 A1 A0
A2 A1 A0
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
1
2.5
2
M0
0
1
0
1
0
1
0
1
0
0
Burst Type
Interleaved
Sequential
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
Mode Register (Mx)
M3 = 0
Address Bus
Address Bus
2
4
8
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 1
2
4
8
7
maining (least significant) address bit(s) is (are) used to
select the starting location within the block. The pro-
grammed burst length applies to both READ and WRITE
bursts.
Burst Type
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
by the burst length, the burst type and the starting col-
umn address, as shown in Burst Definition Table.
NOTE: 1. For a burst length of two, A1-Ai select the two-
i = 11 for 256MB module, or 12 for 512MB module
Length
Burst
Accesses within a given burst may be programmed to
The ordering of accesses within a burst is determined
2
4
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-pin DDR SDRAM DIMMs
2. For a burst length of four, A2-Ai select the four-
3. For a burst length of eight, A3-Ai select the eight-
4. Whenever a boundary of the block is reached
Starting Column
data-element block; A0 selects the first access
within the block.
data-element block; A0-A1 select the first access
within the block.
data-element block; A0-A2 select the first access
within the block.
within a given sequence above, the following
access wraps within the block.
A2 A1 A0
0
0
0
0
1
1
1
1
256MB, 512MB (ECC x72)
Address
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
Burst Definition
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table
Type = Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Order of Accesses Within a Burst
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
Type = Interleaved
©2002, Micron Technology, Inc.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0