IDT72V2101L15PF IDT, Integrated Device Technology Inc, IDT72V2101L15PF Datasheet - Page 18

• Manufacturer Part Number: IDT72V2101L15PF
• Description: IC FIFO SS 131X18 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V2101L15PF

• Function: Synchronous
• Memory Size: 2.3K (131 x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 2.25Mb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 256Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 55mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V2101L15PF

NOTES:
1. t
2. LD = HIGH.
3. First word latency: t
Q
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH
Q
D
D
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
WCLK
RCLK
0
0
WCLK
0
0
WEN
of WCLK and the rising edge of RCLK is less than t
RCLK
REN
SKEW1
edge of the RCLK and the rising edge of the WCLK is less than t
- Q
- D
WEN
REN
SKEW1
- D
- Q
OE
EF
n
n
n
n
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t
t
ENS
t
DATA IN OUTPUT REGISTER
ENS
SKEW1
TM
t
t
OLZ
t
262,144 x 9, 524,288 x 9
SKEW1
ENH
t
+ 1*T
REF
t
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
A
t
OE
(1)
RCLK
t
SKEW1
+ t
t
t
ENH
ENS
REF
t
DS
t
A
D
(1)
.
1
0
NO WRITE
NO OPERATION
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
t
t
DHS
ENH
SKEW1
LAST WORD
1
, then EF deassertion may be delayed one extra RCLK cycle.
2
t
SKEW1
WFF
, then the FF deassertion may be delayed one extra WCLK cycle.
t
t
OHZ
t
DS
t
DS
ENS
t
CLKH
D
D
1
NO OPERATION
X
t
WFF
t
t
ENH
DH
DATA READ
18
t
t
DH
CLK
2
t
CLKL
t
CLKH
t
REF
t
ENS
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
ENS
t
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
REF
WFF
2
). If the time between the rising edge
). If the time between the rising
TEMPERATURE RANGES
NEXT DATA READ
t
ENS
t
WFF
t
DS
D
0
D
X
+1
t
REF
t
t
ENH
A
4669 drw 10
t
DH
t
4669 drw 11
WFF
D
1