IDT72V2101L15PF IDT, Integrated Device Technology Inc, IDT72V2101L15PF Datasheet - Page 22
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IDT72V2101L15PF
Manufacturer Part Number
IDT72V2101L15PF
Description
IC FIFO SS 131X18 15NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V2111L15PFGI.pdf
(27 pages)
Specifications of IDT72V2101L15PF
Function
Synchronous
Memory Size
2.3K (131 x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
2.25Mb
Access Time (max)
10ns
Word Size
9b
Organization
256Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V2101L15PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V2101L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2101L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2101L15PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2101L15PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. X = 17 for the IDT72V2101 and X = 18 for the IDT72V2111.
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
3. OE = LOW
4. W
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
Q
WCLK
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
WCLK
RCLK
0
procedure. D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111.
SEN
WEN
REN
- Q
PAE
PAF
LD
1
OR
, W
SI
RT
HF
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
TM
262,144 x 9, 524,288 x 9
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
LDS
t
ENS
DS
t
ENS
t
RTS
t
RTS
t
t
ENH
LDH
W
x+1
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
SKEW2
Figure 12. Retransmit Timing (FWFT Mode)
1
2
t
PAF
1
t
A
t
BIT X
REF
22
(1)
t
ENS
W
BIT 0
1
(4)
2
t
A
t
PAE
FULL OFFSET
W
2
(4)
3
t
A
COMMERCIAL AND INDUSTRIAL
W
3
TEMPERATURE RANGES
(4)
t
BIT X
LDH
t
t
ENH
DH
(1)
4
t
A
W
4669 drw 16
4669 drw 15
4
t
ENH