IDT72V2101L15PF IDT, Integrated Device Technology Inc, IDT72V2101L15PF Datasheet - Page 23
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IDT72V2101L15PF
Manufacturer Part Number
IDT72V2101L15PF
Description
IC FIFO SS 131X18 15NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V2111L15PFGI.pdf
(27 pages)
Specifications of IDT72V2101L15PF
Function
Synchronous
Memory Size
2.3K (131 x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
2.25Mb
Access Time (max)
10ns
Word Size
9b
Organization
256Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V2101L15PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V2101L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2101L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2101L15PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2101L15PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
NOTE:
1. OE = LOW
D
Q
WCLK
RCLK
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
WCLK
WEN
0
RCLK
0
REN
In IDT Standard mode: D = 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111.
In FWFT mode: D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111.
RCLK and the rising edge of WCLK is less than t
PAF
WEN
SKEW2
REN
- D
- Q
LD
LD
7
7
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKH
DATA IN OUTPUT REGISTER
PAE OFFSET
t
t
CLKH
CLKH
(LSB)
TM
t
t
CLK
CLK
262,144 x 9, 524,288 x 9
t
t
ENS
t
t
LDS
ENS
LDS
t
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
DS
t
t
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENS
CLKL
CLKL
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
t
CLKL
A
t
t
t
t
ENH
PAE OFFSET
LDH
t
ENH
DH
(MID-BYTE)
LDH
t
ENH
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
PAE OFFSET
(LSB)
1
(2)
PAE OFFSET
(MSB)
P A E O F F S E T
( M I D - B Y T E )
2
23
t
PAF
PAF OFFSET
(LSB)
t
ENS
PAE OFFSET
t
SKEW2
(MSB)
(3)
PAF OFFSET
(MID-BYTE)
t
ENH
D - m words in FIFO
PAF OFFSET
1
(LSB)
COMMERCIAL AND INDUSTRIAL
PAF OFFSET
(2)
PAF
(MSB)
). If the time between the rising edge of
PAF OFFSET
(MID-BYTE)
TEMPERATURE RANGES
2
t
PAF
t
A
t
t
ENH
t
LDH
t
ENH
LDH
t
DH
D-(m+1) words
in FIFO
PAF OFFSET
4669 drw 19
4669 drw 17
4669 drw 18
(MSB)
(2)