HMP525F7FFP4C-xx Hynix Semiconductor, HMP525F7FFP4C-xx Datasheet - Page 19
![no-image](/images/manufacturer_photos/0/3/320/hynix_semiconductor_sml.jpg)
HMP525F7FFP4C-xx
Manufacturer Part Number
HMP525F7FFP4C-xx
Description
240pin Fully Buffered DDR2 SDRAM DIMMs
Manufacturer
Hynix Semiconductor
Datasheet
1.HMP525F7FFP4C-XX.pdf
(26 pages)
Rev 1.2 / Feb. 2009
Timing Parameters
Note:
1. Defined in FB-DIMM Architecture and Protocol Spec.
Environmental Parameters
Note:
1. The designer must meet the case temperature specifications for individual module components.
2. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and
device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating
conditions for extended periods
EI Assertion Pass-Thru Timing
EI Deassertion Pass-Thru Timing
EI Assertion Duration
Bit Lock Interval
Frame Lock Interval
Symbol
H
T
T
H
P
P
OPR
OPR
STG
BAR
BAR
STG
Parameter
Operating temperature
Operating humidity(relative)
Storage temperature
Storage humidity(without condensation)
Barometric pressure(operating)
Barometric pressure (storage)
Parameter
tEI Propagad
tFrameLock
Symbol
tBitLock
tEID
tEI
1
240pin Fully Buffered DDR2 SDRAM DIMMs
Min
100
-50 to +100
Typ
See Note
10 to 90
Rating
5 to 95
-
15240
3050
bit lock
Max
119
154
4
Units
%
o
%
m
m
C
frames
frames
Unit
clks
clks
clks
Notes
Note
1
2
2
2
2
2
1
1
1
-
-
19