CLA80000 Zarlink Semiconductor, CLA80000 Datasheet - Page 8

• Manufacturer Part Number: CLA80000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

THERMAL MANAGEMENT
I Low power CMOS for better thermal management
I 1.3 µ W per gate per MHz (3V supply)
I High pinout power packages available
The increase in speed and density available through
advanced CMOS processes, results in a corresponding
increase in power dissipation. SemiCustom designers now
have the ability to design circuits of 260,000 gates and over,
and chip power consumption is a very important concern.
The logic core of 260k plus gates is the dominant factor in
power dissipation at this complexity. It is essential to offer
ultra low power core logic to maintain an acceptable overall
chip power budget.
To minimize this problem Zarlink’s CLA80k arrays offer low
power factors and a selection of power packages.
Dissipation of 1.3 µ W per gate per MHz (3V supply) is lower
than most competitive arrays, with the reduced junction
temperatures having the added advantage of improved
performance and reliability.
CLA80k POWER DISSIPATION CALCULATION
CLA80k series power dissipation for any array can be
estimated by following the example for the CLA87XXX at a
typical voltage of 5V.
8
Number of available gates
Gates used
Gates switching
Power dissipation/gate/MHz ( µ W)
(gate fanout typically 2 loads, at 5V)
Frequency (MHz)
Total core dissipation (mW)
Number of I/O pads used as Outputs
Outputs switching each cycle
Dissipation/output buffer/MHz/pF ( µ W)
Output loading in pF
Output buffer power (mW)
Total Power at 10MHz clock rate (W)
157872
40%
15%
4.1
10
388
122
20%
25
50
305
0.7
ADVANCED DELAY MODELLING
I Accurate delay calculation
I Edge speed modelling
I Pin to pin timings
I Non-linear delay modelling
I Accurate delay derating
The accuracy of the delay modelling is demonstrated by the
results shown in the table over.
Pin to Pin Delays
Delay models use pin to pin times for both rising and falling
delays between each input and output pin.
The use of pin to pin delays improves simulation accuracy
as there can be considerable variation in delay between
different input pins. For complex gates (e.g. AND-NOR
gates or adders) the variation is up to 40%. For simple
NAND and NOR logic gates the typical variation is 20%.
Non-linear curve fitting
Figure 7 and Figure 8 show the rising and falling delay
through an inverter. For fast input edges (0.5ns) delay time
increases linearly with the output load. For high output
loads delay increases linearly with edge speed. Delay for
slow input edges and light input loads do not follow the
linear model. A simple linear model cannot represent delay
accurately. The following equation is used to model delay
for CLA80k
K
speed set to zero.
K
K
K
light output loadings.
1
2
3
4
Delay
-Delay sensitivity to load.
-Delay sensitivity to input edge speed.
& K
-Intrinsic delay. The delay with load and input edge
5
- These coefficients reduce the effect of edge for
=
K
A
B
C
1
Figure 6 Path dependent delays
+
K
2
Load
+
K
3
Edge
–





---------------------- -
e
K


K
------------------- -
4
Edge
Edge
5
Load
F






