MT28F008B3 Micron, MT28F008B3 Datasheet - Page 4

• Manufacturer Part Number: MT28F008B3
• Description: FLASH MEMORY
• Manufacturer: Micron

PIN DESCRIPTIONS
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
7, 6, 5, 4, 42, 17, 16, 15, 14, 22, 21, 20,
11, 10, 9, 8, 21, 20, 19, 18, 25, 24, 23,
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
35, 34, 3, 2
NUMBERS
41, 40, 39,
38, 37, 36,
15, 17, 19,
21, 24, 26,
16, 18, 20,
22, 25, 27,
28, 30
13, 32
43
12
44
14
33
31
29
23
–
1
–
8, 7, 36, 6, 5, 19, 18, 8, 7,
4, 3, 2, 1, 40, 6, 5, 4, 3, 2,
NUMBERS
25, 26, 27,
28, 32, 33,
13, 37
34, 35
30, 31
23, 39
29, 38
12
22
10
24
11
9
–
–
–
1, 48, 17, 16
NUMBERS
29, 31, 33,
35, 38, 40,
30, 32, 34,
36, 39, 41,
9, 10, 15
42, 44
27, 46
11
14
26
12
28
47
45
43
13
37
SYMBOL
A0–A18/
BYTE#
DQ15/
(A - 1)
DQ14
(A19)
DQ0–
DQ8–
WE#
WP#
DQ7
OE#
CE#
RP#
V
V
V
NC
CC
PP
SS
SMART 3 BOOT BLOCK FLASH MEMORY
Output of address input when BYTE# = LOW during READ or WRITE
Output data input pins during a WRITE. These pins are used to input
Output data input pins during a WRITE when BYTE# = HIGH. These
Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB
Input/ Data I/Os: Data output pins during any READ operation or
Input/ Data I/Os: Data output pins during any READ operation or
Input
Input
Input
Input
Input
Input
Input
TYPE
–
4
Write Enable: Determines if a given cycle is a WRITE cycle. If
WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if V
V
ERASE. Does not affect WRITE or ERASE operation on other
blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status register,
sets the internal state machine (ISM) to the array read mode
and places the device in deep power-down mode. All inputs,
including CE#, are “Don’t Care,” and all outputs are High-Z.
RP# unlocks the boot block and overrides the condition of
WP# when at V
other modes of operation.
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active through
DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are High-Z, and all
data is accessed through DQ0–DQ7. DQ15/(A - 1) becomes the
least significant address input.
Address Inputs: Select a unique 16-bit word or 8-bit byte. The
DQ15/(A - 1) input becomes the lowest order address when
BYTE# = LOW (MT28F800B3) to allow for a selection of an 8-
bit byte from the 1,048,576 available.
operation.
commands to the CEL.
pins are High-Z when BYTE# is LOW.
until completion of the WRITE or ERASE, V
(3.3V) or V
operations.
No Connect: These pins may be driven or left unconnected.
PPH
1
(3.3V) or V
PPH
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(5V). V
HH
PPH
(12V), and must be held at V
2
(5V) and RP# = V
PP
= “Don’t Care” during all other
DESCRIPTION
IH
during a WRITE or
PP
must be at V
IH
©2001, Micron Technology, Inc.
during all
8Mb
PP
=
PPH
1