MT28F320J3 Micron, MT28F320J3 Datasheet - Page 24

• Manufacturer Part Number: MT28F320J3
• Description: Q-FLASHTM MEMORY
• Manufacturer: Micron

ing the PROGRAM SUSPEND command requests that
the ISM suspend the program sequence at a predeter-
mined point in the algorithm. When the PROGRAM
SUSPEND command is written, the device continues
to output status register data when read. Polling status
register bit SR7 can determine when the programming
operation has been suspended. When SR7 = 1, SR2 is
also set to “1” to indicate that the device is in the pro-
gram suspend mode. STS in RY/BY# level mode also
transitions to V
suspend latency.
read data from unsuspended locations. While pro-
gramming is suspended, the only other valid com-
mands are READ QUERY, READ STATUS REGISTER,
CLEAR STATUS REGISTER, CONFIGURE, and
PROGRAM RESUME. When the PROGRAM RESUME
command is written, the ISM continues the program-
ming process. Status register bits SR2 and SR7 auto-
matically clear and STS in RY/BY# mode returns to V
After the PROGRAM RESUME command is written, the
device automatically outputs status register data when
read. V
valid V
programming) while in program suspend mode. Refer
to Figure 6 (PROGRAM SUSPEND/RESUME Flowchart).
SET READ CONFIGURATION COMMAND
CONFIGURATION command. The devices default to
the asynchronous page mode. If this command is given,
the operation of the device will not be affected.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
Hence, a READ ARRAY command can be written to
Q-Flash memory does not support the SET READ
PEN
CC
levels (the same V
must remain at V
OH
. Note that
PENH
PEN
t
LPS defines the program
and V
and V
CC
CC
must remain at
levels used for
OL
.
24
READ CONFIGURATION
nous page mode and standard word/byte READs with-
out configuration requirement. Status register and
identifier only support standard word/byte single
READ operations.
STS CONFIGURATION COMMAND
can be configured to different states. Once configured,
the STS pin remains in that configuration until another
configuration command is issued, RP# is asserted LOW,
or the device is powered down. Initially, the STS pin
defaults to RY/BY# operation where RY/BY# goes LOW
to indicate that the state machine is busy. When HIGH,
RY/BY# indicates that either the state machine is ready
for a new operation or it is suspended. Table 18, Con-
figuration Coding Definitions, shows the possible STS
configurations. To change the STS pin to other modes,
the CONFIGURATION command is given, followed by
the desired configuration code. The three alternate
configurations are all pulse modes and may be used as
a system interrupt. With these configurations, bit 0
controls erase complete interrupt pulse, and bit 1 con-
trols program complete interrupt pulse. Providing the
00h configuration code with the CONFIGURATION
command resets the STS pin to the default RY/BY#
level mode. Table 18 describes possible configurations
and usage. The CONFIGURATION command can only
be given when the device is not busy or suspended.
When configured in one of the pulse modes, the STS
pin pulses LOW with a typical pulse width of 250ns.
Check SR7 for device status. An invalid configuration
code results in status register bits SR4 and SR5 being
set to “1.”
Micron’s Q-Flash devices support both asynchro-
Using the CONFIGURATION command, the STS pin
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
©2002, Micron Technology, Inc.