MT28F320J3 Micron, MT28F320J3 Datasheet - Page 8

• Manufacturer Part Number: MT28F320J3
• Description: Q-FLASHTM MEMORY
• Manufacturer: Micron

MEMORY ARCHITECTURE
memory array architecture is divided into one hun-
dred twenty-eight, sixty-four, or thirty-two 128KB
blocks, respectively (see Figure 1). The internal archi-
tecture allows greater flexibility when updating data
because individual code portions can be updated in-
dependently of the rest of the code.
03FFFFh
020000h
01FFFFh
000000h
BUS OPERATION
conform to the standard microprocessor bus cycles.
The local CPU reads and writes Flash memory in-
system.
READ
tifier codes, or status register, regardless of the V
voltage. The device automatically resets to read array
mode upon initial device power-up or after exit from
reset/power-down mode. To access other read mode
commands (READ ARRAY, READ QUERY, READ IDEN-
TIFIER CODES, or READ STATUS REGISTER), these
commands should be issued to the CUI. Six control
pins dictate the data flow in and out of the device: CE0,
CE1, CE2, OE#, WE#, and RP#. In system designs using
multiple Q-Flash devices, CE0, CE1, and CE2 (CEx)
select the memory device (see Table 2). To drive data
out of the device and onto the I/O bus, OE# must be
active and WE# must be inactive (V
device defaults to asynchronous page mode, thus pro-
viding a high data transfer rate for memory subsystems.
In this state, data is internally read and stored in a
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
FFFFFFh
FE0000h
7FFFFFh
7E0000h
3FFFFFh
3E0000h
The MT28F128J3, MT28F640J3, and MT28F320J3
All bus cycles to and from the Flash memory must
Information can be read from any block, query, iden-
When reading information in read array mode, the
Byte-Wide (x8) Mode
128KB Block
128KB Block
128KB Block
128KB Block
128KB Block
A0–A23: 128Mb
A0–A22: 64Mb
A0–A21: 32Mb
Memory Map
127
63
31
1
0
Figure 1
7FFFFFh
7F0000h
3FFFFFh
3F0000h
1FFFFFh
1F0000h
01FFFFh
010000h
00FFFFh
000000h
64K-Word Block
64K-Word Block
64K-Word Block
64K-Word Block
64K-Word Block
Word-Wide (x16) Mode
A1–A23: 128Mb
A1–A22: 64Mb
A1–A21: 32Mb
IH
).
127
63
31
1
0
PEN
8
NOTE: For single-chip applications, CE2 and CE1 can be
high-speed page buffer. A0–A2 select data in the page
buffer. Asynchronous page mode, with a page size of
four words or eight bytes, is supported with no addi-
tional commands required.
OUTPUT DISABLE
HIGH level (V
High-Z.
STANDBY
Table 2) and place it in standby mode, which substan-
tially reduces device power consumption. DQ0–DQ15
outputs are placed in High-Z, independent of OE#. If
deselected during block erase, program, or lock bit con-
figuration, the ISM continues functioning and consum-
ing active power until the operation completes.
RESET/POWER-DOWN
mode when set to V
output drivers in High-Z, and turns off internal cir-
cuitry. RP# must be held LOW for a minimum of
t
initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The com-
mand execution logic (CEL) is reset to the read array
mode and the status register is set to 80h.
tion, RP# LOW aborts the operation. In default mode,
STS transitions LOW and remains LOW for a maximum
time of
complete. Any memory content changes are no longer
RWH is required after return from reset mode until
The device outputs are disabled with OE# at a logic
CE0, CE1, and CE2 can disable the device (see
RP# puts the device into the reset/power-down
During read, RP# LOW deselects the memory, places
During block erase, program, or lock bit configura-
CE2
V
V
V
V
V
V
V
V
IH
IH
IH
IH
connected to GND.
IL
IL
IL
IL
t
PLPH +
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Chip Enable Truth Table
IH
). Output pins DQ0–DQ15 are placed in
t
CE1
PHRH, until the RESET operation is
V
V
V
V
V
V
V
V
128Mb, 64Mb, 32Mb
IH
IH
IH
IH
IL
IL
IL
IL
IL
.
Table 2
Q-FLASH MEMORY
CE0
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
IL
©2002, Micron Technology, Inc.
Disabled
Disabled
Disabled
Disabled
DEVICE
Enabled
Enabled
Enabled
Enabled
t
PLPH.