MT9044AP1 Zarlink Semiconductor, Inc., MT9044AP1 Datasheet - Page 2

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MT9044AP1

Manufacturer Part Number
MT9044AP1
Description
Framer: Framer Circuit: T1/E1/OC3 System Synchronizer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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Description
The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing
and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links.
The MT9044 generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz,
or 8kHz input reference.
The MT9044 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced, and
Stratum 4; and ETSI ETS 300 011; and ITU-T G.813 Option 1 for 2048 kbit/s interfaces. It will meet the jitter/wander
tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope,
holdover frequency and MTIE requirements for these specifications.
AVDD
OSCo
C1.5o
OSCi
F16o
VDD
RSP
VSS
TSP
F0o
F8o
10
11
12
13
14
15
16
17
7
8
9
18 19 20 21 22 23 24
6
5
4 3
MT9044AP
2
1
44
25 26 27 28
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RSEL
IC
TDO
MS1
MS2
LOS1
LOS2
GTo
VSS
GTi
HOLDOVER
Figure 2 - Pin Connections
Zarlink Semiconductor Inc.
MT9044
2
OSCo
AVDD
C1.5o
OSCi
F16o
VDD
RSP
VSS
TSP
F0o
F8o
10
11
1
2
3
4
5
6
7
8
9
12 13 14 15 16 17 18
44
43
42 41
MT9044AL
40
39
38
19 20 21 22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Data Sheet
RSEL
IC
TDO
MS1
MS2
LOS1
LOS2
GTo
VSS
GTi
HOLDOVER

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