MT90820AL1 Zarlink Semiconductor, Inc., MT90820AL1 Datasheet - Page 11

• Manufacturer Part Number: MT90820AL1
• Description: Large Digital Switch
• Manufacturer: Zarlink Semiconductor, Inc.

MT90820
Data Sheet
The microprocessor interface automatically identifies the type of micro-processor bus connected to the MT90820.
This circuit uses the level of the DS/RD input pin at the rising edge of AS/ALE to identify the appropriate bus timing
connected to the MT90820. If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed timing is
selected. If DS/RD is high at the rising edge of AS/ALE, then the mode 2 multiplexed bus timing is selected.
For multiplexed operation, the required signals are the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15),
Address strobe/Address latch enable (AS/ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR), Chip
select (CS) and Data transfer acknowledge (DTA). See Figure 13 and Figure 14 for multiplexed parallel microport
timing.
For the Motorola non-multiplexed bus, the required signals are the 16-bit data bus (AD0-AD7, D8-D15), 8-bit
address bus (A0-A7) and 4 control lines (CS, DS, R/W and DTA). See Figure 15 for Motorola non-multiplexed
microport timing.
The MT90820 microport provides access to the internal registers, connection and data memories. All locations
provide read/write access except for the data memory and the frame alignment register which are read only.
Memory Mapping
The address bus on the microprocessor interface selects the internal registers and memories of the MT90820. If
the A7 address input is low, then the control (CR), interface mode selection (IMS), frame alignment (FAR) and
frame input offset (FOR) registers are addressed by A6 to A0 according to Table 4.
If the A7 is high, then the remaining address input lines are used to select memory subsections of up to 128
locations corresponding to the maximum number of channels per input or output stream. The address input lines
and the stream address bits (STA) of the control register allow access to the entire data and connection memories.
The control and IMS registers together control all the major functions of the device. The IMS register should be
programmed immediately after system power-up to establish the desired switching configuration as explained in the
Serial Data Interface Timing and Switching Configurations sections.
The control register is used to control switching operations in the MT90820. It selects the internal memory locations
that specify the input and output channels selected for switching.
The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS)
and the stream address bits (STA). The memory block programming bit allows users to program the entire
connection memory block, (see Memory Block Programming section). The memory select bit controls the selection
of the connection memory or the data Memory. The stream address bits define an internal memory subsections
corresponding to input or output ST-BUS streams.
The data in the IMS register consists of block programming bits (BPD0-BPD4), block programming enable bit
(BPE), output stand by bit (OSB), start frame evaluation bit (SFE) and data rate selection bits (DR0, DR1). The
block programming and the block programming enable bits allows users to program the entire connection memory,
(see Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all
ST-BUS output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all ST-BUS output drivers
are enabled.
Connection Memory Control
The contents of the CSTo bit of each connection memory location are output on the CSTo pin once every frame.
The CSTo pin is a 4.096, 8.192 or 16.384 Mb/s output, which carries 512, 1,024 or 2,048 bits, respectively. If the
CSTo bit is set high, the corresponding bit on the CSTo output is transmitted high. If the CSTo bit is low, the
corresponding bit on the CSTo output is transmitted low. The contents of the CSTo bits of the connection memory
are transmitted sequentially on to the CSTo pin and are synchronous with the data rates on the other ST-BUS
streams.
The CSTo bit is output one channel before the corresponding channel on the ST-BUS. For example, in 2 Mb/s
mode, the contents of the CSTo bit in position 0 (STo0, CH0) of the connection memory is output on the first clock
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Zarlink Semiconductor Inc.