MT90820AL1 Zarlink Semiconductor, Inc., MT90820AL1 Datasheet - Page 16
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MT90820AL1
Manufacturer Part Number
MT90820AL1
Description
Large Digital Switch
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT90820AL1.pdf
(37 pages)
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Part Number:
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10 - 0
Bit
15
0
ST-BUS Frame
Read Address:
Reset Value:
Offset Value
Offset Value
GCI Frame
FE Input
14
FE Input
0
CLK
CLK
FD10-0
Name
13
0
CFE
12
Figure 3 - Example for Frame Alignment Measurement
Table 10 - Frame Alignment (FAR) Register Bits
FD11
11
Frame Delay Bits. The binary value expressed in these bits refers to the measured
input offset value. These bits are reset to zero when the SFE bit of the IMS register
changes from 1 to 0. (FD10 = MSB, FD0 = LSB)
0
02
0000
0
H
FD10
1
,
10
1
H
.
2
2
FD9
Zarlink Semiconductor Inc.
9
3
3
MT90820
4
FD8
4
8
16
5
5
(FD[10:0] = 06
(FD11 = 0, sample at CLK low phase)
FD7
7
6
6
7
7
FD6
6
Description
H
8
8
(FD[10:0] = 09
(FD11 = 1, sample at CLK high phase)
)
FD5
9
5
9
10
10
FD4
4
H
11
11
)
12
FD3
12
3
13
13
FD2
2
14
14
15
FD1
15
1
16
Data Sheet
FD0
0