MT9196AS Zarlink Semiconductor, Inc., MT9196AS Datasheet - Page 32
MT9196AS
Manufacturer Part Number
MT9196AS
Description
Integrated Digital Phone Circuit (IDPC)
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT9196AS.pdf
(46 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
MT9196AS
Manufacturer:
MITEL
Quantity:
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Part Number:
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Manufacturer:
ZARLINK
Quantity:
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MT9196
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing.
* Note: RxINC, refer to Control Register 2, address 0Fh.
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing.
* Note: RxINC and TxINC, refer to Control Register 2, address 0Fh.
7-166
AC Characteristics
(V
AC Electrical Characteristics
1
2
3
4
5
6
7
8
9
Ref
1
=1.0 volts and V
Analog output at the CODEC
full scale
Absolute half-channel gain
PCM to HSPKR
PCM to SPKR
PCM to AUXout
Tolerance at all other receive
filter settings (-1 to -7dB)
Gain tracking vs. input level
CCITT G.714 Method 2
Signal to total distortion vs.
input level
CCITT G.714 Method 2
Receive Idle Channel Noise
Gain relative to gain at 1020Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz
Absolute Delay
Group Delay relative to D
Crosstalk
Absolute path gain
Gain adjust = 0dB
All other settings
(-9.96 to +9.96dB)
Characteristics
Characteristics
Bias
=2.5 volts.)
A/D to D/A
D/A to A/D
†
for D/A (Receive) Path
AR
†
for Side-tone Path
G
G
Sym
G
G
A
A
CT
CT
Sym
G
G
G
G
AS
AS
G
G
G
N
N
D
D
AS1
AS2
Lo3.17
Lo3.14
AR1
AR2
AR3
AR4
QR
CR
PR
RR
AR
DR
TR
RT
TR
-17.2
-14.7
Min
-0.3
-0.3
-13.1
-10.6
-0.25
-0.90
Min
-1.0
-0.2
-0.3
-0.6
-1.6
-14
35
29
24
- 0dBm0 = 1.421V
-16.7
-14.2
Typ
5.704
5.906
-12.1
-78.5
Typ
-9.6
240
750
380
130
750
-12
13
‡
0
‡
-16.2
-13.7
Max
+0.3
+0.3
-11.1
-12.5
Max
+0.2
15.5
0.25
0.25
0.25
-8.6
1.0
-10
0.3
0.6
1.6
-77
-25
-74
-80
rms
for -Law and 1.477V
Units
dB
dB
dB
dB
dBrnC0
dBm0p
Units
Vp-p
Vp-p
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
s
s
s
s
s
TxINC, RxINC both 0*
TxINC, RxINC both 1*
M inputs to HSPKR outputs
1000 Hz
SIDEA/u=0
SIDEA/u=1
from nominal
relative measurements w.r.t.
G
AS1
A-Law
Receive filter gain = 0dB
setting. Digital gain = 0dB
setting.
RxINC = 0*
RxINC = 1*
@1020 Hz
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
0 to -30 dBm0
-40 dBm0
-45 dBm0
A-Law
at frequency of min. delay
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
G.714.16
& G
-Law
-Law
Test Conditions
rms
Test Conditions
AS2
for A-Law, at the CODEC.