IDT72V2113L7-5BCI IDT, Integrated Device Technology Inc, IDT72V2113L7-5BCI Datasheet - Page 15

• Manufacturer Part Number: IDT72V2113L7-5BCI
• Description: IC FIFO SYNC 3.3V 5NS 100-LBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V2113L7-5BCI

• Function: Synchronous
• Memory Size: 4.7Mb (262k x 18)
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 5ns
• Word Size: 18/9Bit
• Organization: 256Kx18/512Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 133.3MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 35mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V2113L7-5BCI; 800-1513

IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
IDT72V2103/72V2113
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
6th Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q8
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q8
1st Parallel Offset Write/Read Cycle
16
16
8
8
15
EMPTY OFFSET REGISTER
15
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
7
7
FULL OFFSET REGISTER
FULL OFFSET REGISTER
FULL OFFSET REGISTER
14
14
6
6
13
13
5
5
⎯
x9 Bus Width
12
12
4
4
Figure 3. Programmable Flag Offset Programming Sequence
11
19
19
11
3
3
18
10
18
10
2
2
17
17
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
1
9
1
9
TM
NARROW BUS FIFO
TM
15
D/Q17
D/Q17
D/Q17
NARROW BUS FIFO
D/Q17
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
IDT72V2103/72V2113
D/Q16
D/Q16
D/Q16
D/Q16
16
16
15
16
15
16
15
14
15
14
14
13
14
13
EMPTY OFFSET (LSB) REGISTER
FULL OFFSET (MSB) REGISTER
EMPTY OFFSET (MSB) REGISTER
FULL OFFSET (LSB) REGISTER
13
13
12
12
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
12
11
12
11
# of Bits Used:
18 bits for the IDT72V2103
19 bits for the IDT72V2113
Note: All unused bits of the
LSB & MSB are don’t care
17 bits for the IDT72V2103
18 bits for the IDT72V2113
Note: All unused bits of the
LSB & MSB are don’t care
10
10
# of Bits Used:
11
11
10
10
9
9
All Other Modes
x9 to x9 Mode
4666 drw 06
D/Q8
D/Q8
9
9
⎯
8
8
8
8
x18 Bus Width
7
7
7
7
6
6
6
6
# of Bits Used
5
5
5
5
COMMERCIAL AND INDUSTRIAL
4
4
4
4
3
3
3
3
18
18 17
18
18 17
2
2
2
2
TEMPERATURE RANGES
D/Q0
D/Q0
D/Q0
D/Q0
17
17
1
1
1
1
Non-Interspersed
Parity
Interspersed
Parity
JUNE 1, 2010
6119 drw 06