MT8888CN Zarlink Semiconductor, Inc., MT8888CN Datasheet - Page 3

• Manufacturer Part Number: MT8888CN
• Description: Integrated DTMF Transceiver with Intel Micro Interface
• Manufacturer: Zarlink Semiconductor, Inc.

Functional Description
The
consists of a high performance DTMF receiver with
an internal gain setting amplifier and a DTMF
generator which employs a burst counter to
synthesize precise tone bursts and pauses. A call
progress mode can be selected so that frequencies
within the specified passband can be detected. The
Intel micro interface allows microcontrollers, such as
the 8080, 80C31/51 and 8085, to access the
MT8888C internal registers.
Input Configuration
The input arrangement of the MT8888C provides a
differential-input operational amplifier as well as a
bias source (V
V
feedback resistor to the op-amp output (GS) for gain
adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.
Figure 4 shows the necessary connections for a
differential input configuration.
Receiver Section
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). These
filters incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
DD
Figure 3 - Single-Ended Input Configuration
VOLTAGE GAIN
(A
/2. Provision is made for connection of a
V
) = R
C
MT8888C
F
/ R
IN
R
Ref
IN
), which is used to bias the inputs at
Integrated
R
F
DTMF
IN+
IN-
GS
V
Ref
Transceiver
MT8888C
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 k
R2 = 60k , R3 = 37.5 k
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(A
INPUT IMPEDANCE
(Z
F
Figure 4 - Differential Input Configuration
Table 1. Functional Encode/Decode Table
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
V
IN
LOW
diff) = 2 R1
diff) - R5/R1
C2
C1
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
R4
R1
0= LOGIC LOW, 1= LOGIC HIGH
F
HIGH
2
R3
+ (1/ C)
DIGIT
2
C
D
A
B
1
2
3
4
5
6
7
8
9
0
#
*
R2
R5
D
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
3
MT8888C
D
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
2
IN+
IN-
GS
V
Ref
MT8888C
D
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
D
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
3