ST8016T Sitronix Technology, ST8016T Datasheet - Page 3

• Manufacturer Part Number: ST8016T
• Description: COM/SEG LCD Driver
• Manufacturer: Sitronix Technology

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3
4
Active Control
SP Conversion
& Data Control
Data Latch Control
Data Latch
Line Latch/
Shift Register
Level Shifter
4-Level Driver
Control Logic
Preliminary Ver 0.12
/DISPOFF
BLOCK
EIO
XCK
EIO
S/C
L/R
MD
FR
LP
1
2
BLOCK DIAGRAM
FUNCTIONAL OPERATIONS OF EACH BLOCK
SHIFTER
In case of segment mode, controls the selection or non-selection of the chip.
Following an LP signal input, and after the chip selection signal is input, a selection signal is
generated internally until 160 bits of data have been read in.
Once data input has been completed, a selection signal for cascade connection is output, and
the chip is non-selected.
In case of common mode, controls the input/output data of bi-directional pins.
In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel input
mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel input mode
in latch circuit; after that they are put on the internal data bus 8 bits at a time.
In case of segment mode, selects the state of the data latch which reads in the data bus
signals. The shift direction is controlled by the control logic. For every 16 bits of data read in,
the selection signal shifts one bit based on the state of the control circuit.
In case of segment mode, latches the data on the data bus. The latch state of each LCD
drive output pin is controlled by the control logic and the data latch control; 160 bits of data are
read in 20 sets of 8 bits.
In case of segment mode, all 160 bits which have been read into the data latch are
simultaneously latched at the falling edge of the LP signal, and are output to the level shifter
block. In case of common mode, shifts data from the data input pin at the falling edge of the LP
signal.
The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to the
driver block.
Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4
levels (V
Controls the operation of each block. In case of segment mode, when an LP signal has been
input, all blocks are reset and the control logic waits for the selection signal output from the
active control block. Once the selection signal has been output, operation of the data latch and
data transmission is controlled, 160 bits of data are read in, and the chip is non-selected. In
case of common mode, controls the direction of data shift.
LEVEL
CONTROL
CONTROL
DI0
ACTIVE
LOGIC
0
SP CONVERSION & DATA CONTROL
, V
V
DI1
0R
12
, V
DI2
V
(4 to 8 or 8 to 8)
12R
43
DI3
or V
8
V
43R
DI4
SS
V
) based on the S/C, FR and /DISPOFF signals.
DI5
SS
DI6
Page 3/27
16
LATCH
DATA
Y
8 BIT
1
DI7
16
160-BIT LINE LATCH/SHIFT REGISTER
Y
2
160-BIT 4-LEVEL DRIVER
160-BIT LEVEL SHIFTER
DATA LATCH CONTROL
FUNCTION
160
160
Y
159
16
V
DD
Y
160
V
SS
V
V
V
V
SS
43L
12L
0L
2007/10/29
ST8016T