CYNCP80192 Cypress Semiconductor, CYNCP80192 Datasheet - Page 12

• Manufacturer Part Number: CYNCP80192
• Description: Network Database Coprocessor
• Manufacturer: Cypress Semiconductor

6.0
6.1
The network processor(s) access the NDC using the coprocessor (SSRAM) interface. The NDC has a CFG and status registers
area and an operating registers area, as shown in Table 6-1.
Table 6-1. Register Partitions for Coprocessor Access
The CFG area shown in Table 6-2 is used for programming the NDC via a 64-bit CFG register.
Table 6-2. Configuration and Status Registers Area
6.2
6.2.1
The 64-bit CFG register contains the following fields, as shown in Table 6-3.
Table 6-3. Configuration Register
SRST. This active high bit resets the state of the device. The reset bit will be active for 32 CLK cycles and will be automatically
cleared after the reset has taken effect.
Table Size (TLSZ). This determines the NSE CFG for the specific table size.
Latency of Hit Signals (HLAT). This determines the data access latency of associated data SSRAM.
CPCFG. This field sets the width of the processor and context IDs that will be driven on the CPID bus after the completion of the
operation. The contents of the CPID bus are generated by concatenating LSBs of the processor ID and the LSBs of the context ID.
Notes:
Document #: 38-02043 Rev. *B
4.
5.
6.
7.
ADR
0–1
ADR[9] = 1
The resulting registers of the context descriptors are Read-only.
Once the NDC is configured, the network processors will use the operating registers area to configure the NSEs, initialize and manage the protocol layer tables,
and perform searches through such tables.
Though the NDC does not program the NSE with this information, the coprocessor uses it to determine the duration of operations such as Search and Learn.
(More details on this field can be found in the data sheets for CYNSE70XXX NSEs.)
Though the NDC does not program the NSE with this information, the coprocessor uses it to determine the duration of operations such as Search and Read
from the SSRAMs. (More details on this field can be found in the data sheet on CYNSE70XXX NSEs.)
512–1023
Address
0–511
Coprocessor Interface Register
Configuration and Status Registers
Configuration Register
00: CPID[7:0] = {processor ID[2:0], context ID[4:0]}.
01: CPID[7:0] = {processor ID[3:0], context ID[3:0]}.
10: CPID[7:0] = {processor ID[4:0], context ID[2:0]}.
11: Reserved.
Registers
Reserved
63–12
Address
10–511
CFG and Status
Registers
Operating Registers
0–1
2–3
4–5
6–7
8–9
Abbreviation
Transceiver
External
Present
11
Search Result
Bit in Data
Field
Type
R/W
R/W
10
CFG Register
Error, Status Registers (Read-only)
Mask Registers
Reserved
Information Registers (Read-only)
Reserved
Configuration Register [63:0]
These registers are for configuring the NDC (Read/Write), reporting the
error code in the status register (Read-only), setting up the mask register
for asserting INTR (Read/Write), and obtaining information on the device
(Read-only).
Dynamic access for searches and table management happens through this
area of the coprocessor address space.
INTR_Polarity
9
Configuration and Status Registers Area
SSRAM
Present
[6]
8
Description
CPCFG
[4]
7–6
[5]
[7]
HLAT
5–3
CYNCP80192
TLSZ
2–1
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SRST
0