CYNCP80192 Cypress Semiconductor, CYNCP80192 Datasheet - Page 18

• Manufacturer Part Number: CYNCP80192
• Description: Network Database Coprocessor
• Manufacturer: Cypress Semiconductor

Result Registers 0 and 1 return the result of the Read operation in two 64-bit words.
Table 7-4. Read Command
Write Command (01 H). Table 7-5 shows the format for the Write command. The Write command’s structure is wr(ADR, dt). The
Write command uses three 64-bit words in the context descriptor: command word, Data 0 word and Data 1 word. The Write
command is issued through the command descriptor. The Write access location could be either the data array, mask array, NSE
register or associative SSRAM connected to the NSE. Bits 15–0 of the Data 0 word contain the Write address. Bits 23–19 of the
Data 0 supply the SEID. The Data 1 word contains the data bits [67:4], while the data bits [3:0] (called layer bits for Data 1) are
passed in the command descriptor word.
Table 7-5. Write Command
Search Command (02H). The Search command’s structure is se(dt0) for 68-bit word, se(dt0,dt1) for 136-bit word and
se(dt0,dt1,dt2,dt3) for 272-bit word. The Search command uses two, three, or five 64-bit words in the context descriptor depending
upon the size of the search entry (68-bit, 136-bit, or 272-bit). The search size is encoded in the command word, bits [26:25]. Data
bits [3:0] for each 68-bit NSE word are stored in the command word in layer attribute bits for Data 0 through Data 3. The number
of layer attribute bits used in the command word depends upon the search size. Thus, for a 68-bit search the descriptor command
bits [11:8] will be used; for a 136-bit search, bits [15:8] will be used and for a 272-bit search, bits [23:8] will be used. The indices
for SSR, GMR, and comparand register are stored in the command word also. (For further explanation of these indices, refer to
data sheets for the CYNSE70XXX NSEs.)
Successive search operations are pipelined. For a 64-bit network processor interface running at 100 MHz, the NDC can sustain
33 Msps for tables configured as ×68 bit in the NSEs. For ×136-bit CFG, the performance will be 25 Msps, and for ×272-bit CFG,
the peak performance will be 16.67 Msps. For a 32-bit network processor Interface, the peak performance will drop by a factor
of one half compared to the performance of the 64-bit interface.
7.3.2
For the Search command these words contain the search key that will be presented to the NSEs. Table 7-6 shows the meaningful
fields for each search size that are driven on the NSE bus DQ from the descriptors.The data driven on the DQ[3:0] for various
searches is picked from the command word as follows.
Table 7-6. Search Data
Result Registers 0 and 1 return the result of the search operation.
Learn Command (03H). The Learn command’s structure is le(indx). The Learn command will use two 64-bit words (command
descriptor word and Data 0) in the context descriptor. The command includes an index for a Comparand register of the NSE,
where the data to be Learnt was stored by a prior search instruction. Data 0 contains the data to be written in associative SRAM.
Learn will result in error if the Learn is performed when the NSE SE_FULL is high. The error bit in the result register will indicate
the error. The Learn error will be set in the error and status register.
Move Command (04 H). The Move command’s structure is mv(addr1, addr2, len). The Move command utilizes two 64-bit words
in the context descriptor: command descriptor word, and Data 0 word. Bits 15–0 of the Data 0 word will contain the source address;
bits 23–19 will contain the SEID; bits 39–24 will contain the destination address, bits 47–43 will contain the destination SEID; and
bits 56–48 will contain the move block length (see Table 7-7). Current implementation restricts the maximum move block length
to 256 words (of 68-bit each) in between/within the NSE(s). The minimum length for the Move command is four locations.
Document #: 38-02043 Rev. *B
Search Size
Address
Address
Data 0
Data 1
Data 0
Context Descriptor Data 0–Data 3
68-bit search: layer attribute and valid bits for Data 0.
136-bit search: layer attribute and valid bits for Data 0 and Data 1.
272-bit search: layer attribute and valid bits for Data 0, Data 1, Data 2, and Data 3.
00
01
10
11
Data 0 — DQ[67:4] (Cycle A and B)
Data 0 — DQ[67:4] (Cycle A), Data 1 — DQ[67:4] (Cycle B)
Data 0 — DQ[67:4] (Cycle A), Data 1 — DQ[67:4] (Cycle B)
Data 2 — DQ[67:4] (Cycle C), Data 3 — DQ[67:4] (Cycle D)
Reserved
Reserved
63–24
Reserved
63–24
23–19
SEID
23–19
SEID
Meaningful Data (64 bits each)
Data [67: 4]
Reserved
18–16
Reserved
18–16
Address Pointer
Address Pointer
CYNCP80192
15–0
15–0
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