AD9517-0 Analog Devices, Inc., AD9517-0 Datasheet - Page 11

• Manufacturer Part Number: AD9517-0
• Description: 12-output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Parameter
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
LVDS OUTPUT ADDITIVE TIME JITTER
CMOS OUTPUT ADDITIVE TIME JITTER
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
LVDS OUTPUT ADDITIVE TIME JITTER
CMOS OUTPUT ADDITIVE TIME JITTER
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1
CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2; VCO Divider Not Used
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
CLK = 1.6 GHz; LVDS= 100 MHz; Divider = 16
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
Divider = 12; Duty-Cycle Correction = Off
Divider = 12; Duty-Cycle Correction = Off
Min
Min
Typ
124
176
259
Typ
210
285
350
Rev. 0 | Page 11 of 80
Max
Max
Unit
f
f
f
Min
S
S
S
rms
rms
rms
Unit
f
f
f
S
S
S
rms
rms
rms
Typ
40
80
215
245
85
113
280
365
Test Conditions/Comments
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method
Distribution section only; does not include PLL and VCO;
rising edge of clock signal
Calculated from SNR of ADC method
Distribution section only; does not include PLL and VCO;
rising edge of clock signal
Calculated from SNR of ADC method
Max
Unit
f
f
f
f
f
f
f
f
S
S
S
S
S
S
S
S
rms
rms
rms
rms
rms
rms
rms
rms
Test Conditions/Comments
Distribution section only; does not
include PLL and VCO; rising edge of
clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method;
DCC not used for even divides
Calculated from SNR of ADC method;
DCC on
Distribution section only; does not
include PLL and VCO; rising edge of
clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method;
DCC not used for even divides
Distribution section only; does not
include PLL and VCO; rising edge of
clock signal
Calculated from SNR of ADC method;
DCC not used for even divides
AD9517-0