AD9517-0 Analog Devices, Inc., AD9517-0 Datasheet - Page 5

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AD9517-0

Manufacturer Part Number
AD9517-0
Description
12-output Clock Generator With Integrated 2.8 Ghz Vco
Manufacturer
Analog Devices, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9517-0ABCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Parameter
PHASE/FREQUENCY DETECTOR (PFD)
CHARGE PUMP (CP)
PRESCALER (PART OF N DIVIDER)
PLL DIVIDER DELAYS
NOISE CHARACTERISTICS
PFD Input Frequency
Antibacklash Pulse Width
I
I
Sink-and-Source Current Matching
I
I
Prescaler Input Frequency
Prescaler Output Frequency
000
001
010
011
100
101
110
111
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Means Within the LBW
of the PLL)
PLL Figure of Merit (FOM)
CP
CP
CP
CP
High Value
Low Value
Absolute Accuracy
CP
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
@ 500 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
Sink/Source
High Impedance Mode Leakage
vs. CP
vs. Temperature
RSET
Range
V
Min
Typ
1.3
2.9
6.0
4.8
0.60
2.5
2.7/10
1
2
1.5
2
Off
330
440
550
660
770
880
990
−165
−162
−151
−143
−220
Rev. 0 | Page 5 of 80
Max
100
45
300
600
900
600
1000
2400
3000
3000
300
Unit
MHz
MHz
ns
ns
ns
mA
mA
%
nA
%
%
%
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
0x17<1:0> = 01b
0x17<1:0> = 00b; 0x17<1:0> = 11b
0x17<1:0> = 10b
Programmable
With CP
CP
0.5 < CP
0.5 < CP
CP
A, B counter input frequency (prescaler
input frequency divided by P)
Register 0x19: R <5:3>, N <2:0>; see Table 53
The PLL in-band phase noise floor is estimated
by measuring the in-band phase noise at the
output of the VCO and subtracting 20 log(N)
(where N is the value of the N divider)
Reference slew rate > 0.25 V/ns. FOM +10 log(f
is an approximation of the PFD/CP in-band
phase noise (in the flat region) inside the PLL
loop bandwidth; when running closed loop,
the phase noise, as observed at the VCO output,
is increased by 20 log(N)
V
V
= V
= V
CP
CP
RSET
V
V
/2 V
/2 V
< V
< V
= 5.1 kΩ
CP
CP
− 0.5 V
− 0.5 V
AD9517-0
PFD
)

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