AD9517-0 Analog Devices, Inc., AD9517-0 Datasheet - Page 37

• Manufacturer Part Number: AD9517-0
• Description: 12-output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

DIGITAL LOCK DETECT (DLD)
By selecting the proper output through the mux on each pin,
the DLD function is available at the LD, STATUS, and
REFMON pins. The digital lock detect circuit indicates a lock
when the time difference of the rising edges at the PFD inputs is
less than a specified value (the lock threshold). The loss of a
lock is indicated when the time difference exceeds a specified
value (the unlock threshold). Note that the unlock threshold is
wider than the lock threshold, which allows some phase error in
excess of the lock window to occur without chattering on the
lock indicator.
The lock detect window timing depends on three settings: the
digital lock detect window bit (0x18<4>), the antibacklash pulse
width setting (0x17<1:0>, see Table 2), and the lock detect
counter (0x18<6:5>). A lock is not indicated until there is a
programmable number of consecutive PFD cycles with a time
difference less than the lock detect threshold. The lock detect
circuit continues to indicate a lock until a time difference
greater than the unlock threshold occurs on a single subsequent
cycle. For the lock detect to work properly, the period of the
PFD frequency must be greater than the unlock threshold. The
number of consecutive PFD cycles required for lock is
programmable (0x18<6:5>).
Analog Lock Detect (ALD)
The AD9517 provides an ALD function that may be selected for
use at the LD pin. There are two versions of ALD:
• N-channel open-drain lock detect. This signal requires a
• P-channel open-drain lock detect. This signal requires a pull-
The analog lock detect function requires an R-C filter to
provide a logic level indicating lock/unlock.
Current Source Digital Lock Detect (DLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is possible by using the
pull-up resistor to the positive supply, VS. The output is
normally high with short, low-going pulses. Lock is indicated
by the minimum duty cycle of the low-going pulses.
down resistor to GND. The output is normally low with
short, high-going pulses. Lock is indicated by the minimum
duty cycle of the high-going pulses.
Figure 48. Example of Analog Lock Detect Filter Using
ALD
AD9517-0
N-Channel Open-Drain Driver
LD
R1
V
S
= 3.3V
R2
C
V
OUT
Rev. 0 | Page 37 of 80
current source lock detect function. This function is set by
selecting it as the output from the LD pin control (0x1A<5:0>).
The current source lock detect provides a current of 110 μA
when DLD is true and shorts to ground when DLD is false.
If a capacitor is connected to the LD pin, it charges at a rate
determined by the current source during the DLD true time
but is discharged nearly instantly when DLD is false. By
monitoring the voltage at the LD pin (top of the capacitor), it is
only possible to get a Logic High level after the DLD has been
true for a sufficiently long time. Any momentary DLD false
resets the charging. By selecting a properly sized capacitor, it is
possible to delay a lock detect indication until the PLL is stably
locked, and the lock detect does not chatter.
The voltage on the capacitor can be sensed by an external
comparator connected to the LD pin. However, there is an
internal LD pin comparator that can be read at the REFMON
pin control (0x1B<4:0>) or the STATUS pin control (0x17<7:2>)
as an active high signal. It is also available as an active low signal
(REFMON, 0x1B<4:0> and STATUS, 0x17<7:2>). The internal
LD pin comparator trip point and hysteresis are given in Table 16.
External VCXO/VCO Clock Input (CLK/ CLK )
CLK is a differential input that can be used as an input to drive
the AD9517 clock distribution section. This input can receive
up to 2.4 GHz. The pins are internally self-biased, and the input
signal should be ac-coupled via capacitors.
The CLK/ CLK input can be used either as a distribution only
input (with the PLL off), or as a feedback input for an external
VCO/VCXO using the internal PLL when the internal VCO is
not used. The CLK/ CLK input can be used for frequencies up
to 2.4 GHz.
CLK
CLK
VS
COMPARATOR
AD9517-0
Figure 50. CLK Equivalent Input Circuit
Figure 49. Current Source Lock Detect
LD PIN
110µA
2.5kΩ
5kΩ
5kΩ
DLD
2.5kΩ
LD
REFMON
OR
STATUS
CLOCK INPUT
STAGE
C
V
OUT
AD9517-0