AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet - Page 61

• Manufacturer Part Number: AD9517-1
• Description: 12-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
10
10
10
10
11
12
13
14
15
16
16
16
Table 53. PLL
<7>
<6:4> CP Current
<3:2> CP Mode
<1:0> PLL Power-
<7:0> 14-Bit
<5:0> 14-Bit
<5:0> 6-Bit
<7:0> 13-Bit
<4:0> 13-Bit
<7>
<6>
<5>
PFD Polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only.
Down
R Divider
Bits<7:0>
(LSB)
R Divider
Bits<13:8>
(MSB)
A Counter
B Counter
Bits<7:0>
(LSB)
B Counter
Bits<12:8>
(MSB)
Set CP Pin
to V
Reset R
Counter
Reset A and B Reset A and B counters (part of N divider).
Counters
CP
/2
Description
The on-chip VCO requires positive polarity <7> = 0.
<7> = 0; positive (higher control voltage produces higher frequency).
<7> = 1; negative (higher control voltage produces lower frequency).
Charge pump current (with CPRSET = 5.1 kΩ).
<6> <5>
0
0
0
0
1
1
1
1
Charge pump operating mode.
<3>
0
0
1
1
PLL operating mode.
<1>
0
0
1
1
R divider LSBs—lower eight bits.
R divider MSBs—upper six bits.
A counter (part of N divider).
B counter (part of N divider)—lower eight bits.
B counter (part of N divider)—upper five bits.
Set the CP pin to one-half of the V
<7> = 0; CP normal operation.
<7> = 1; CP pin set to V
Reset R counter (R divider).
<6> = 0; normal.
<6> = 1; reset R counter.
<5> = 0; normal.
<5> = 1; reset A and B counters.
0
0
1
1
0
0
1
1
0
1
<2>
1
0
<0>
0
1
0
1
<4>
0
1
0
1
0
1
0
1
Charge Pump Mode
High impedance state.
Force source current (pump up).
Force sink current (pump down).
Normal operation.
Mode
Normal operation.
Asynchronous power-down.
Normal operation.
Synchronous power-down.
CP
/2.
I
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8
CP
(mA)
CP
Rev. 0 | Page 61 of 80
supply voltage.
AD9517-1