AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet - Page 62

• Manufacturer Part Number: AD9517-1
• Description: 12-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
16
16
16
17
AD9517-1
<4>
<3>
<2:0> Prescaler P
<7:2> STATUS
Reset All
Counters
B Counter
Bypass
Pin Control
Description
Reset R, A, and B counters.
<4> = 0; normal.
<4> = 1; reset R, A, and B counters.
B counter bypass. This is valid only when operating the prescaler in FD mode.
<3> = 0; normal.
<3> = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for
the N divider.
Prescaler: DM = dual modulus and FD = fixed divide.
<2>
0
0
0
0
1
1
1
1
Select the signal that is connected to the STATUS pin
<7>
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
<1> <0> Mode
0
0
1
1
0
0
1
1
<6> <5> <4>
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
FD
FD
DM
DM
DM
DM
DM
FD
<3>
0
0
1
1
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Prescaler
Divide-by-1.
Divide-by-2.
Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0.
Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.
Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.
Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0.
Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0.
Divide-by-3.
<2>
0
1
0
1
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Rev. 0 | Page 62 of 80
Level or
Dynamic
Signal
LVL
DYN
DYN
DYN
DYN
DYN
DYN
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Signal at STATUS Pin
Ground (dc).
N divider output (after the delay).
R divider output (after the delay).
A divider output.
Prescaler output.
PFD up pulse.
PFD down pulse.
Ground (dc); for all other cases of 0XXXXX not specified.
The selections that follow are the same as REFMON.
Ground (dc).
REF1 clock (differential reference when in differential mode).
REF2 clock (N/A in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available in differential
mode).
Status of selected reference (status of differential reference);
active high.
Status of unselected reference (not available in differential
mode); active high.
Status REF1 frequency (active high).
Status REF2 frequency (active high).
(Status REF1 frequency) AND (status REF2 frequency).
(DLD) AND (status of selected reference) AND (status of VCO).
Status of VCO frequency (active high).
Selected reference (low = REF1, high = REF2).
Digital lock detect (DLD); active high.
Holdover active (active high).
LD pin comparator output (active high).
VS (PLL supply).