AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet - Page 76

• Manufacturer Part Number: AD9517-1
• Description: 12-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
1E0
1E1
1E1
1E1
Reg.
Addr
(Hex) Bit(s)
19F
1A0
1A0
1A1
1A1
1A1
1A1
1A1
1A1
1A2
AD9517-1
Table 59. VCO Divider and CLK Input
<2:0> VCO Divider
<4>
<3>
<2>
<3:0> Phase Offset Divider 3.1
<7:4> Low Cycles Divider 3.2
<3:0> High Cycles Divider 3.2
<5>
<4>
<3>
<2>
<1>
<0>
<0>
Power-Down Clock Input Section Power down the clock input section (including CLK buffer, VCO divider, and CLK tree).
Power-Down VCO Clock Interface Power down the interface block between VCO and clock distribution.
Power-Down VCO and CLK
Name
Bypass Divider 3.2
Bypass Divider 3.1
Divider 3 Nosync
Divider 3 Force High
Start High Divider 3.2
Start High Divider 3.1
Divider 3 DCCOFF
Description
Refer to LVDS/CMOS channel divider function description.
Number of clock cycles of 3.2 divider input during which 3.2 output stays low.
Number of clock cycles of 3.2 divider input during which 3.2 output stays high.
Bypass (and power-down) 3.2 divider logic, route clock to 3.2 output.
<5> = 0; do not bypass.
<5> = 1; bypass.
Bypass (and power-down) 3.1 divider logic, route clock to 3.1 output.
<4> = 0; do not bypass.
<4> = 1; bypass.
Nosync.
<3> = 0; obey chip-level SYNC signal.
<3> = 1; ignore chip-level SYNC signal.
Force Divider 3 output high. Requires that nosync also be set.
<2> = 0; force low.
<2> = 1; force high.
Divider 3.2 start high/low.
<1> = 0; start low.
<1> = 1; start high.
Divider 3.1 start high/low.
<0> = 0; start low.
<0> = 1; start high.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
<2>
0
0
0
0
1
1
1
1
<4> = 0; normal operation.
<4> = 1; power-down.
<3> = 0; normal operation.
<3> = 1; power-down.
<2> = 0; normal operation.
<2> = 1; power-down.
Description
Power down both VCO and CLK input.
Rev. 0 | Page 76 of 80
<1>
0
0
1
1
0
0
1
1
<0>
0
1
0
1
0
1
0
1
Divide
2
3
4
5
6
Output static
Output static
Output static