AD9516-5 Analog Devices, Inc., AD9516-5 Datasheet

AD9516-5

Manufacturer Part Number

AD9516-5

Description

14-output Clock Generator

Manufacturer

Analog Devices, Inc.

Datasheet

1.AD9516-5.pdf (76 pages)

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FEATURES

Low phase noise, phase-locked loop

Six 1.6 GHz LVPECL outputs arranged in 3 groups

Four 800 MHz LVDS clock outputs arranged in 2 groups

Automatic synchronization of all outputs on power-up

Manual synchronization of outputs as needed

SPI-compatible serial control port

64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC,

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

ATE and high performance instrumentation

GENERAL DESCRIPTION

The AD9516-5

with subpicosecond jitter performance, along with an on-chip PLL

that can be used with an external VCO/VCXO.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

The AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-5 is used, it refers to that specific member of the AD9516 family.

Supports external VCO/VCXO to 2.4 GHz

1 differential or 2 single-ended reference inputs

Accepts CMOS, LVDS, or LVPECL references to 250 MHz

Reference monitoring capability

Auto and manual reference switchover/holdover modes

Glitch-free (hitless) switchover between references

Automatic recovery from holdover

Programmable delays in path to PFD

Digital or analog lock detect, selectable

Each group shares 1 to 32 dividers with coarse phase delay

Additive output jitter: 225 fs rms

Channel-to-channel skew paired outputs: <10 ps

Each group shares 2 cascaded 1-to-32 dividers with coarse

Additive output jitter: 275 fs rms

Fine delay adjust (ΔT) on each LVDS output

Each LVDS output can be configured as 2 CMOS outputs

and other 10 Gbps protocols

with selectable revertive/nonrevertive switching

phase delay

(for f

OUT

≤ 250 MHz)

provides a multioutput clock distribution function

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

The AD9516-5 emphasizes low jitter and phase noise to

maximize data converter performance and is suitable for other

applications with demanding phase noise and jitter requirements.

The AD9516-5 features six LVPECL outputs in three groups,

along with four LVDS outputs in two groups. Any LVDS output

can be reconfigured as two CMOS outputs. The LVPECL outputs

operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and

the CMOS outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide ratio

and coarse delay (or phase) to be set. The range of division for

the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow

a range of divisions up to a maximum of 1024.

The AD9516-5 is available in a 64-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated by

connecting the charge pump supply (VCP) to 5.5 V. A separate

LVPECL power supply can be from 2.375 V to 3.6 V.

The AD9516-5 is specified for operation over the standard

industrial range of −40°C to +85°C.

For applications requiring an integrated EEPROM, or needing

additional outputs, the

REFIN

CLK

14-Output Clock Generator

FUNCTIONAL BLOCK DIAGRAM

SERIAL CONTROL PORT

DIV/Φ

REF1

REF2

DIGITAL LOGIC

AND

AD9520-5

AND MUXs

DIVIDER

DIV/Φ

Figure 1.

ΔT

and

LVPECL

LVDS/CMOS

AD9516-5

AD9522-5

MONITOR

STATUS

AD9516-5

www.analog.com

are available.

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

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