ZEN2044F Zenic, ZEN2044F Datasheet
ZEN2044F
Related parts for ZEN2044F
ZEN2044F Summary of contents
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... UD/AB2 DIR2 Vdd EXTB3 EXTA3 Vss LD3 LT3 Vss Vdd SEL30 SEL31 SEL32 Vss A/UP3 B/DN3 Z/CLR3 Vdd n.c. 100 - 1 - ZEN2044F can count ZEN2044F can be used in a variety of ZEN2044F Pin Configuration(Top View ...
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... EXTA2 B C/D c EXT EXTB2 LT3 LD LD3 SEL[2:0] SEL3[2:0] UD/AB UD/AB3 DIR DIR3 A/UP A/UP3 B/DN B/DN3 Z/CLR Z/CLR3 D[7: ZEN2044F Mode0,1 EXTA EXTA0 function EXTB EXTB0 control Comparator A(24bit) Comparator B(24bit) Latch reg.(24bit) cnt0 Ch.1 CE EXTA EXTA1 C/D c EXTB EXTB1 ...
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... AD/CE1 and AD/CE0 are used to select the channnel. I The DRCTCE specifies the mode of the channel select. I The C/D defines the type of the data transfered between the CPU and the ZEN2044F(command or value). This pin is usually connected with LSB of the address lines. I The RD is the strobe signal of the read operation. I The WR is the strobe signal of the write operation ...
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... The condition of these three pins(SEL 0, SEL 1 and SEL 2) specifies the counter operation mode. See the Table The DIR selects the count direction of the up/down counter. I The UD/AB selects the input pulse mode(up/down or not Ground(0V ZEN2044F Function Z2044G00 ZENIC INC. ) ...
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... N. 100 TEST0 47 TEST1 48 TESTI 13 Note ) Except N.C., the input pins which are not used MUST be connected with Vdd or Ground. I/O - Supply voltage(+5V) - Not connected. I These test pins MUST be connected with +5V in nomal operation ZEN2044F Function ZEN2044F ( Z2044G00 ZENIC INC. ) ...
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... Write: data for registers(ch. Write: data for registers(ch. Read: status register(ch. Read: status register(ch. Read: status register(ch. Read: status register(ch. Write: command(ch. Write: command(ch. Write: command(ch. Write: command(ch.3) ( Z2044G00 ZENIC INC. has following ZEN2044F ) ...
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... Write: data for registers(ch. Write: data for registers(ch. Read: status register(ch. Read: status register(ch. Read: status register(ch. Read: status register(ch. Write: command(ch. Write: command(ch. Write: command(ch. Write: command(ch.3) ( Z2044G00 ZENIC INC. and ZEN2044F ZEN2044F ) ...
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... Command mode The has the following two system modes. First of all necessary to determine which ZEN2044F mode you use(Mode 0 or Mode 1). The system mode is fixed by executing the system mode set command (90H or 91H). 4-2-1. Mode 0 [after executing command(90H) or system reset] EXTB n is set as a universal input terminal U ...
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... Double 1 0 Quad 1 1 Single pulse input A B Single 1 0 Double 1 1 Note ) B is used as the count enable signal Z2044G00 ZENIC INC. ZEN2044F ) ...
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... When the line-noises are sampled, the Fig.1 State transitions and an example of detecting the abnormal input mark) or not. detects the abnormal transition. ZEN2044F ZEN2044F mark) occurs, the Abnormal Input AI(00->11) ( Z2044G00 ZENIC INC. ) ...
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... Note ) The counter value can be directly wrote without storing it in the preload register but we don't recommend it. Table 6 Regsiter/Mode The reset value System mode Mode 0 Reference reg. keeping the value A before reset Reference reg. keeping the value B before reset (NOP) ZNE (NOP) Up/down counter Low byte - 11 - ZEN2044F ZEN2044F ( Z2044G00 ZENIC INC. ) ...
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... Before you write a data to a certain register, you should set an access pointer properly. But the has an auto-incremental function of the access pointer. So when you write data in the ZEN2044F following sequence, what you have to set is only a starting point. Also when reading the latch register, the target byte(low, middle or high) is changed automatically ...
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... ZE1 ZE0 LT The BS1 and BS0 determine the target byte(high byte, middle ZEN2044F. ZEN2044F HeX Operation 90 Mode 0 select[default] 91 Mode 1 select n is set as a universal input U. n can be programed. Please refer to Mode1 RS1 RS0 BS1 BS0 ( Z2044G00 ZENIC INC. ZEN2044F ) ...
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... Command Inhibit(except Command ID) n can be programmed to output one of three signals(EQA ,EQA can be programmed to output one of three signals(EQB ,INTEQB n and EQB . ZEN2044F Operation EQB INTAI ). n n output and initializes the phase ZEN2044F ( Z2044G00 ZENIC INC ...
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... Inhibit n n EQB -> EXTB [default] n INTEQA command reset n n INTEQB , INTAI command reset n n INTAI -> EXTB disabling n n INTAI -> EXTB enabling INTEQA -> EXTA n n disabling n n INTEQA -> EXTA enabling INTEQB -> EXTB n n disabling n n INTEQB -> EXTB enabling ZEN2044F ( Z2044G00 ZENIC INC. ) ...
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... This bit indicates the value of EXTB not sampled but directly monitored. Low Coincident flag of comparator B A value of "0" indicates the data of counter and comparator B is coincident Description n n input that is sampled n input that is sampled n n input. This signal is ( Z2044G00 ZENIC INC. ) ...
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... Two phase-shifted pulse mode(DIR="1") CLK A/UP B/DN CNT (x4) CNT (x2) CNT (x1) EXTB 6-1-2. Single pulse mode(DIR="1") CLK A/UP B/DN CNT (x2) CNT (x1) 6-1-3. Up/down pulse mode(DIR="1") CLK A/UP B/DN CNT are as follows. ZEN2044F n n+1 n+2 n+3 n+4 n+3 n+2 n+1 n n+1 n+2 n n+1 (When INTAI is enabled and AI is detected) n n+1 n+2 n+3 n n ZEN2044F n n n+4 n+2 n ZEN2044F ( Z2044G00 ZENIC INC. ) ...
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... Synchronous mode(Detecting the rising or falling edge of A/UP when Z/CLR is "1" and B/DN is "0") CLK A/UP B/DN Z/CLR CNT 6-3. Loading or latching counter value 6-3-1. External loading or latching CLK LD LT LDR CNT LTR counting up/down 0 counting up/down counting up/down counting up/down a ZEN2044F ( Z2044G00 ZENIC INC. ) ...
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... Detecting coincidence 6-4-1. Momentary coincident output CLK CMPRA CNT EXTA 6-4-2. Hold coincident output CLK CMPRA CNT EXTA Note ) EXTB has the same timing as EXTA in Mode 1. n n-1 n n+1 n n ZEN2044F ( Z2044G00 ZENIC INC. ) ...
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... Max Vdd 4.75 5.00 5.25 Topr 0 - +70 Symbol Conditions Vih Vil Iih Vin=Vdd Iil Vin=Vss Voh Ioh=-4mA Vol Iol=4mA Idds Vin=Vdd or Vss Iddo - 20 - Unit °C Unit V °C Min Max Unit 2.2 V 0 2 ZEN2044F ( Z2044G00 ZENIC INC. ) ...
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... PWAB SAB AHL *2+16 ACY *2+16 UDCY ZEN2044F ( Z2044G00 ZENIC INC. Unit ...
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... Single pulse input timing n A/ B/DN 7-5-3. Up/down pulse input timing n A/UP n B/DN T CYAB T T PWAB PWAB SAB SAB SAB SAB T T PWAB PWAB T CYAB AHL AHL T SS ACY UDCY UDCY ( Z2044G00 ZENIC INC. ZEN2044F ) ...
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... CLK 7-5-7. System reset timing RESET WR, 7-5-8. Load pulse input timing LD n 7-5-9. Latch pulse input timing RST RSRC T LDW T LTW - WRC RRC Z2044G00 ZENIC INC. WA ZEN2044F ) ...
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... Note ) At executing Mode 1 select command(EXTB is changed from input into output) CLK EXTB n Note ) At executing Mode 0 select command(EXTB is changed from output into input) 8. Package Outlines output timing T EXF T SEB n T FEB n 23.8+-0.3 20.0+-0 100 0.3+-0.1 0.575TYP 1 0.65 0.15 0.8+-0 0.13 M (Unit : mm) ( Z2044G00 ZENIC INC. ZEN2044F ) ...
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... ZENIC products could create a situation where personal injury or death may occur. All rights reserved. Copyright 2000 ZENIC Inc. ZEN2044F ZENIC Inc. URL http://www.zenic.co.jp/ 1-17-14, Ogaya Otsu Shiga 520-2144, JAPAN Fax ...