ZEN2044F Zenic, ZEN2044F Datasheet - Page 16

• Manufacturer Part Number: ZEN2044F
• Description: 33MHz Up/down Counter
• Manufacturer: Zenic

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5-5. Status register
method of reading out this register.
The status register is used to monitor internal conditions. Please refer to "4-1. CPU Interface" for the
D7
D6
D5
D4
D3
D2
D1
D0
Bit
AI
Z
A
B
DTR
U/D
EQA
U
[Mode 0]
EQB
[Mode 1]
Symbol
High
None
None
None
High
None
Low
None
Low
Active
Table 10 Format of status register
Abnormal input detection flag(only phase-shifted pulse input)
Z/CLR input monitor
A/UP
B/DN
Data ready flag of the latch register
Direction of counting
Coincident flag of comparator A
Universal input U(EXTB ) input monitor
Coincident flag of comparator B
A value of "1" indicates that the abnormal transition state of
phase shifted inputs is detected.
This bit indicates the value of Z/CLR input that is sampled
at the rising edge of CLK.
This bit indicates the value of A/UP
at the rising edge of CLK.
This bit indicates the value of B/DN
at the rising edge of CLK.
A value of "1" indicates the counter data has been transfered
to the latch register. This flag is cleared by reading the data
of the latch register.
The current counting direction is indicated. "1" means up
count and "0" means down count.
A value of "0" indicates the data of counter and comparator A
is coincident.
This bit indicates the value of EXTB
not sampled but directly monitored.
A value of "0" indicates the data of counter and comparator B
is coincident.
n
n
n
input monitor
input monitor
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n
Description
n
n
n
n
input that is sampled
input that is sampled
input. This signal is
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Z2044G00 ZENIC INC.
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