DS42515 AMD, DS42515 Datasheet - Page 8

• Manufacturer Part Number: DS42515
• Description: MCP Flash Memory and SRAM
• Manufacturer: AMD

PIN DESCRIPTION
A0–A17
A–1, A18–A19 = 3 Address Inputs (Flash)
SA
DQ0–DQ15
CE#f
CE#s
OE#
WE#
RY/BY#
UB#s
LB#s
CIOf
CIOs
RESET#
WP#/ACC
V
V
V
NC
ORDERING INFORMATION
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The r egis ter is a l atch us ed to s tore th e
commands, along with the address and data informa-
tion needed to execute the command. The contents of
8
CC
CC
SS
f
s
Order Number
DS42515
= 18 Address Inputs (Common)
= Highest Order Address Input
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
= Chip Enable (SRAM)
= Output Enable (Common)
= Write Enable (Common)
= Ready/Busy Output
= Upper Byte Control (SRAM)
= Lower Byte Control (SRAM)
= I/O Configuration (Flash)
= I/O Configuration (SRAM)
= Hardware Reset Pin, Active Low
= Hardware Write Protect/
= Flash 3.0 volt-only single power sup-
= SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
(SRAM) Byte mode
CIOf = V
CIOf = V
CIOs = V
CIOs = V
Acceleration Pin (Flash)
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
Valid Combination
IH
IL
IH
IL
= Byte mode (x8)
= Word mode (x16),
= Byte mode (x8)
= Word mode (x16),
Package Marking
DS42515
DS42515
LOGIC SYMBOL
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Tables 1 through 3 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections de-
scribe each of these operations in further detail.
18
A–1, A18–A19
SA
CE#f
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#s
LB#s
CIOf
CIOs
A0–A17
DQ0–DQ15
RY/BY#
16 or 8