LTC1401 Linear Technology, LTC1401 Datasheet - Page 12

• Manufacturer Part Number: LTC1401
• Description: Complete SO-8/ 12-Bit/ 200ksps ADC with Shutdown
• Manufacturer: Linear Technology

LTC1401
12
APPLICATIONS
circuitry. In this mode, the ADC draws only 1.5mW of
power instead of 15mW (for minimum power, the logic
inputs must be within 500mV of the supply rails). The
wake-up time from Nap mode to active mode is 350ns. In
Sleep mode, power consumption is reduced to 19.5 W by
cutting off the supply to the comparator and reference.
Figure 11 illustrates power-down methods for the LTC1401.
The chip enters Nap mode by keeping the CLK signal low
and pulsing the CONV signal twice. For Sleep mode
operation, CONV signal should be pulsed four times while
CLK is kept low. NAP and SLEEP modes are activated on
the falling edge of the CONV pulse. By pulling SHDN low,
the LTC1401 enters Shutdown mode and power con-
sumption drops to 13.5 W.
Once SHDN goes high, the LTC1401 returns to active
mode or the LTC1401 returns to active mode by pulsing
the CLK signal if the device has entered Nap/Sleep mode.
During the transistion from Sleep mode to active mode,
the V
conditions. With a 10 F bypass capacitor, the wake-up
time from Sleep mode is typically 3ms. A REFRDY signal
is activated once the reference has settled and is ready for
REFRDY
SLEEP
CONV
REF
V
CLK
NAP
REF
voltage ramp-up time is a function of its loading
U
INFORMATION
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS THE FIRST BIT IN THE D
U
W
t
1
Figure 11. Nap Mode and Sleep Mode Waveforms
U
an A/D conversion. This REFRDY bit is sent to the D
as the first bit followed by the 12-bit data word (refer to
Figure 12).
DIGITAL INTERFACE
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the D
the conversion result in serial form.
Figures 12 and 13 show the digital timing waveform of the
LTC1401 during the Analog to Digital Conversion. The
CONV rising edge starts the conversion. Once initiated, it
can not be restarted until the conversion is completed. If
the time from the CONV signal to the CLK rising edge is
less than t
cycle.
The digital output data is updated on the rising edge of the
CLK line. The digital output data consists of a REFRDY bit
followed by the valid 12-bit data word. D
be captured by the receiving system on the rising CLK
edge. Data remains valid for a minimum time of t
the rising CLK edge to allow capture to occur.
2
, the digital output will be delayed by one clock
t
1
OUT
WORD.
OUT
OUT
output provides
data should
LTC1401 • F11
10
OUT
after
pin