LTC1401 Linear Technology, LTC1401 Datasheet - Page 4

• Manufacturer Part Number: LTC1401
• Description: Complete SO-8/ 12-Bit/ 200ksps ADC with Shutdown
• Manufacturer: Linear Technology

TI I G CHARACTERISTICS
LTC1401
SYMBOL
f
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
The
temperature range; all other limits and typicals apply to T
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below GND or above V
will be clamped by internal diodes. This product can handle input currents
greater than 40mA without latch-up if the pin is driven below GND or
above V
Note 4: When these pin voltages are taken below GND, they will be clamped
by internal diodes. This product can handle input currents greater than 40mA
without latch-up if the pin is driven below GND. These pins are not clamped
to V
4
SAMPLE(MAX)
CONV
ACQ
CLK
CLK
WK(NAP)
1
2
3
4
5
6
7
8
9
10
W U
CC
.
denotes specifications which apply over the full operating
CC
.
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time
CLK Frequency
CLK Pulse Width
Time to Wake Up from Nap Mode
CLK Pulse Width to Return to Active Mode
CONV to CLK Setup Time
CONV After Leading CLK
CONV Pulse Width
Time from CLK to Sample Mode
Aperture Delay of Sample-and-Hold
Minimum Delay Between Conversion
Delay Time, CLK to D
Delay Time, CLK to D
Time from Previous Data Remains Valid After CLK
OUT
OUT
Valid
Hi-Z
A
= 25 C.
(Note 5)
CC
, they
Note 5: V
specified.
Note 6: Guaranteed by design, not subject to test.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: The rising edge of CONV starts a conversion. If CONV returns low
at a bit decision point during the conversion, it can create small errors. For
best performance, ensure that CONV returns low either within 120ns after
the conversion starts (i.e., before the first bit decision) or after the 14
clock cycles. (Figure 13 Timing Diagram).
CONDITIONS
f
(Note 6)
(Note 8)
Jitter < 50ps
(Note 6)
C
C
C
CLK
LOAD
LOAD
LOAD
= 3.2MHz
CC
= 20pF
= 20pF
= 20pF
= 3V, f
SAMPLE
= 200kHz, t
MIN
200
100
0.1
60
60
50
15
r
0
= t
f
= 5ns unless otherwise
TYP
315
350
350
80
45
60
60
50
MAX
120
120
550
4.1
3.2
UNITS
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s