LTC1860 Linear Technology, LTC1860 Datasheet - Page 10

• Manufacturer Part Number: LTC1860
• Description: (LTC1860 / LTC1861) 12-/16-Bit 8-Channel 200ksps ADCs
• Manufacturer: Linear Technology

LTC1860/LTC1861
APPLICATIO S I FOR ATIO
10
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1860/LTC1861 should be used with an analog
ground plane and single point grounding techniques. Do
not use wire wrapping techniques to breadboard and
evaluate the device. To achieve the optimum performance,
use a printed circuit board. The ground pins (AGND and
DGND for the LTC1861 MSOP package and GND for the
LTC1860 and LTC1861 SO-8 package) should be tied
directly to the analog ground plane with minimum lead
length.
Bypassing
For good performance, the V
of noise and ripple. Any changes in the V
with respect to ground during the conversion cycle can
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
•
•
•
CONV
SDO
SCK
SDI
*V
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
Figure 5. LTC1861 Transfer Curve
IN
= (SELECTED “+” CHANNEL) –
U
U
t
CONV
CC
and V
W
REF
DON’T CARE
Hi-Z
pins must be free
CC
Figure 4. LTC1861 Operating Sequence
/V
REF
U
SLEEP MODE
voltage
1860 F05
V
IN
*
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
induce errors or noise in the output code. Bypass the V
and V
minimum of 1 F tantalum. Keep the bypass capacitor
leads as short as possible.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1860/
LTC1861 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem if source resistances are less than 200 or high
speed op amps are used (e.g., the LT
LT1807, LT1810, LT1630, LT1226 or LT1215). But if large
source resistances are used, or if slow settling op amps
drive the inputs, take care to ensure the transients caused
by the current spikes settle completely before the conver-
sion begins.
SINGLE-ENDED
DIFFERENTIAL
S/D O/S
MUX MODE
MUX MODE
B11 B10
1
REF
2
B9
pins directly to the analog ground plane with a
3
B8
4
B7
Table 1. Multiplexer Channel Selection
5
SGL/DIFF
B6
6
DON’T CARE
MUX ADDRESS
t
1
1
0
0
B5
SMPL
7
B4
8
B3
9
ODD/SIGN
B2
10
B1
0
1
0
1
11
B0*
12
1860 F04
Hi-Z
CHANNEL #
0
+
+
–
®
1211, LT1469,
1
+
–
+
GND
186465 TBL1
–
–
18601f
CC