LTC1860 Linear Technology, LTC1860 Datasheet - Page 9

• Manufacturer Part Number: LTC1860
• Description: (LTC1860 / LTC1861) 12-/16-Bit 8-Channel 200ksps ADCs
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC1861 OPERATION
Operating Sequence
The LTC1861 conversion cycle begins with the rising edge
of CONV. After a period equal to t
finished. If CONV is left high after this time, the LTC1861
goes into sleep mode. The LTC1861’s 2-bit data word is
clocked into the SDI input on the rising edge of SCK after
CONV goes low. Additional inputs on the SDI pin are then
ignored until the next CONV cycle. The shift clock (SCK)
synchronizes the data transfer with each bit being trans-
mitted on the falling SCK edge and captured on the rising
SCK edge in both transmitting and receiving systems. The
data is transmitted and received simultaneously (full du-
plex). After completing the data transfer, if further SCK
clocks are applied with CONV low, SDO will output zeros
indefinitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
•
•
•
CONV
SDO
SCK
Figure 2. LTC1860 Transfer Curve
U
U
*V
t
CONV
IN
= IN
CONV
+
W
– IN
, the conversion is
–
Hi-Z
Figure 1. LTC1860 Operating Sequence
U
SLEEP MODE
1860 F02
V
IN
*
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table.
In single-ended mode, all input channels are measured
with respect to GND (or AGND). A zero code will occur
when the “+” input minus the “–” input equals zero. Full
scale occurs when the “+” input minus the “–” input
equals V
“–” inputs are sampled at the same time so common
mode noise is rejected. The input span in the SO-8
package is fixed at V
differential mode is grounded, a rail-to-rail input span
will result on the “+” input.
Reference Input
The reference input of the LTC1861 SO-8 package is
internally tied to V
therefore equal to V
of the LTC1861 MSOP package defines the span of the A/
D converter. The LTC1861 MSOP package can operate
with reference voltages from 1V to V
V
IN
REF
= 0V TO V
B11 B10
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER
SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC
WILL OUTPUT ZEROS INDEFINITELY
1
Figure 3. LTC1860 with Rail-to-Rail Input Span
minus 1LSB. See Figure 5. Both the “+” and
2
CC
B9
3
B8
1
2
3
4
CC
CC
4
V
IN
IN
GND
. The span of the A/D converter is
B7
. The voltage on the reference input
REF
5
+
–
LTC1860
REF
B6
t
6
SMPL
LTC1860/LTC1861
CONV
B5
SDO
7
SCK
V
= V
1 F
CC
B4
8
1860 F03
8
7
6
5
CC
B3
9
. If the “–” input in
B2
10
CC
V
B1
11
CC
.
B0*
12
1860 F01
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
Hi-Z
18601f
9