SG175 Motorola / Freescale Semiconductor, SG175 Datasheet - Page 13

• Manufacturer Part Number: SG175
• Description: 68K-ColdFire Product Selector Guide Networking Systems Division 1st Quarter 2000
• Manufacturer: Motorola / Freescale Semiconductor

ZBT
Asynchronous RAMs
CAMs (Content Addressable Memory)
CAMs
Tag RAMs
Tag RAMs
Integrated Cache Solutions
Integrated
Cache
Solutions
Separate and Dual I/O Devices
4M
1M
4M
3M
1M
Category
Category
®
(Zero Bus Turnaround
16K x 64
4K x 64
64K x 18
32K x 72
512K x 9
128K x 36
128K x 9
32K x 36
64K x 18
512K x 8
256K x 16
1M x 4
128K x 24
64K x 18
128K x 8
256K x 4
Organization
Organization
3.3V
3.3V
3.3V
3.3V
5V
3.3V
5V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
3.3V
3.3V
V
V
DD
DD
®
MCM69C432
MCM69C433
MCM69C232
MCM69C233
MCM69T618
MPC2605
MCM67Q909
MCM63D736
MCM67Q709A
MCM69D536
MCM69D618
MCM6946
MCM6343
MCM6949
MCM6341
MCM67A618A
MCM67A618B
MCM6926A
MCM6929A
) RAMs
Device No.
Device No.
(Synchronous)
100
100
100
100
100
241
86
176
86
176
100
36
44
44
32
119
52
52
32
32
Pin
Count
Pin
Count
(Continued)
(TQ) TQFP
(TQ) TQFP
(TQ) TQFP
(TQ) TQFP
(TQ) TQFP
(ZP) PBGA
(ZP) PBGA
(TQ) TQFP
(ZP) PBGA
(TQ) TQFP
(TQ) TQFP
400 (YJ) SOJ
(TS) TSOP
400 (YJ) SOJ
(TS) TSOP
400 (YJ) SOJ
(ZP) PBGA
(FN) PLCC
(FN) PLCC
400 (WJ) SOJ
400 (WJ) SOJ
Package
Package
and Width
in mils
13
20 ns
15 ns
20 ns
15 ns
5 ns
83 / 66 MHz
10.0 / 12.0 ns
4 / 5 ns
10.0 ns
6.0 / 8.0 ns
6.0 / 8.0 ns
10.0 / 12.0 / 15.0 ns
11.0 / 12.0 / 15.0 ns
10.0 / 12.0 / 15.0 ns
10.0 / 11.0 / 12.0 / 15.0 ns
10.0 / 12.0 / 15.0 ns
10 ns
8.0 / 10.0 / 12.0 / 15.0 ns
8.0 / 10.0 / 12.0 / 15.0 ns
Speeds
Speeds
Now
Now
Now
Now
Now
Now
Now
1Q00
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Prod.
Status
Prod.
Status
Dual address, dual I/O. NetRAM.
Not recommended for new designs. EOL status.
Not recommended for new designs. EOL status.
Not recommended for new designs. EOL status.
applications. Industrial temperature available.
Not recommended for new designs. Use MCM67A618B.
General asynchronous, latched address and data
EOL Status – Last Purchase January 2000.
EOL Status – Last Purchase January 2000.
Content addressable memory for communication applica-
tions. 16K connections. 180 ns match time.
66 MHz for PowerQUICC II applications. 240 ns match time.
Content addressable memory for communication applica-
tions. 4K connections. 160 ns match time.
66 MHz for PowerQUICC II applications. 210 ns match time.
100 MHz Data/Tag RAM. For MIPS R5000, Pentium Pro, and
graphics accelerators applications. Not recommended for
new
designs.
Integrated L2 cache for PowerPC processors.One compo-
nent
for 256KB, two for 512KB, and four for 1MB L2 cache solution.
General synchronous separate I/O with write pass through.
3.3 V output levels. Not recommended for new designs.
Dual address, Dual I/O NetRAM pipelined per port chip
enable.
General synchronous separate I/O with write pass through.
3.3 V output levels. Not recommended for new designs.
Dual address, dual I/O. NetRAM.
DSP applications for base stations and other communication
Description
Description