SG175 Motorola / Freescale Semiconductor, SG175 Datasheet - Page 6

• Manufacturer Part Number: SG175
• Description: 68K-ColdFire Product Selector Guide Networking Systems Division 1st Quarter 2000
• Manufacturer: Motorola / Freescale Semiconductor

68K General-Purpose Integrated Processors
68K Integrated Communications Processors
Device No.
MC68306
MC68340
MC68340V
Note: **Extended temperature devices with minimum order requirements. All package/speed combinations may not be valid - consult factory to verify.
Device No.
MC68302
MC68302V
MC68EN302
XC68LC302
XC68LC302V
MC68QH302
MC68360
MC68360V
MC68EN360
MC68EN360V
MC68MH360
MC68MH360
V
MC68606
MC68824
Note: **Extended temperature devices with minimum order requirements. All package/speed combinations may not be valid - consult factory to verify.
Package
144-Lead PV
144-Lead FE
144-Lead PV
144-Lead FT
144-Lead FE
144-Lead PV
Package
132-Lead RC
132-Lead FC
144-Lead PV
144-Lead PV
100-Lead PU
240-Lead EM
357-Lead ZP
241-Lead RC
240-Lead EM
357-Lead ZP
240-Lead EM
357-Lead ZP
241-Lead RC
240-Lead EM
357-Lead ZP
240-Lead EM
357-Lead ZP
241-Lead RC
240-Lead EM
357-Lead ZP
132-Lead FC
144-Lead PV
144-Lead PV
84-Lead FN
84-Lead FN
Speeds
16, 20
16, 20
16, 25
16, 25
16, 25
16 @ 3.3V
16 @ 3.3V
Speeds
16, 20, 25
16, 20, 25
16, 20, 25, 33
16 @ 3.3V
20, 25
16, 20, 25 @ 5V
16, 20 @ 3.3V
16, 20, 25
25,33 @ 5.0V
25 @ 3.3V
25, 33 @ 5.0V
25 @ 3.3V
25,33@5.0V
25@3.3V
12, 16
10, 12, 16
Rev
Rev
B
B
E
E
E
E
E
C
C
C
C
B
B
B
C
K
K
K
K
K
K
K
K
K
C
H
L
L
L
L
L
L
Device Name
Integrated EC000
Processor
Integrated
Processor with
DMA
Device Name
Integrated
Multiprotocol
Processor (IMP)
Integrated
Multiprotocol
Processor with
Ethernet Controller
Low-Cost
Integrated
Multiprotocol
Processor
Quad-HDLC
Integrated
Multiprotocol
Processor
QUICC™
QUad Integrated
Communications
Controller
Multichannel
HDLC Controller
Token Bus
Controller (TBC)
CFC16
CFE16, CFE25
CPV16, CPV25
CFT16, CFT25
CRC16, 20
CFC16, 20
CPV16
CPV16V
CPV20
CPU16, 20
CPU16V
CEM25
CZP25
CRC25
CEM25
CZP25
CRC25
CEM25
CZP25
CRC25
CFN12, 16
Temp**
(-40 to +85 C)
Temp**
(-40 to +85 C)
6
For FC, PV sample —SPAK306FCXXB, SPAK306PVXXB
For PV sample order—KMC68EN302PV25B
For FC, PV sample order—SPAK302FCXXC, SPAK302PVXXC
For PV sample order—KMC68EN302PV25B
For PU sample order—SPAKLC302PUXXB
For PV sample order---SPAKQH302PVXXC
For EM sample order—SPAK360EMXXK, SPAKEN360EMXXK, SPAK360EM25VL,
SPAKEN360EM25VL For ZP sample order—SPAK360ZPXXK, SPAKEN360ZPXXK,
SPAK360ZP25VL, SPAKEN360ZP25VL
For MH sample order—SPAKMH360EMXXK, SPAKMH360EMXXVL, SPAKMH360RLXXK,
SPAKMH360ZPXXK, SPAKMH360ZPXXVL
SOQ
SOQ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
MPQ
MPQ
36
60
60
60
36
60
60
60
84
60
44
44
44
44
44
44
24
24
24
14
24
10
24
24
10
24
24
10
24
1
1
POQ
144
600
POQ
144
300
300
300
420
300
220
220
220
220
220
220
120
120
120
120
120
120
96
60
96
96
60
14
10
10
10
15
15
Brick
Brick
300
300
300
300
300
420
300
120
120
180
Description
68000 CPU, 68681 DUART, DRAM control all in one chip.
CPU32 core processor for data movement applications.
Two channel DMA, two serial channels, two timers, chip
selects, wait-state generation, and glue logic. MC68340V is
the 3.3 volt version of the MC68340.
(FE package not recommended for new designs.)
Description
68000 core with three high-performance multiprotocol
serial channels also on-chip DMA, RAM, timers, I/O, chip
select, and wait state interrupt controller.
Full 68302, plus separate IEEC 802.3 ethernet MAC channel
and full DRAM controller
Static EC000 Core Processor with two high-perfor-
mance multiprotocol serial channels; also on-chip DMA,
RAM, timers, I/O, chip selects, and wait state interrupt
controller.
68302 derivative with support for up to four HDLC
transparent channels. Pin compatible with 68302.
CPU32 + core with System Integration Module (SIM) and
four high-performance SCCs support numerous protocols.
Two SCCs support Ethernet on "EN" version.
One-chip integrated microprocessor and peripheral combi-
nation with four SCCs, two serial management controllers
(SMCs) and one serial peripheral interface (SPI).
Implements CCITT Q.920/Q.921 link access procedure
(LAPB) specified at ISO level 2 for both signaling and data
applications in an ISDN.
Implements IEEE 802.4 Token Bus Media Access Control
which GM MAP specifies in layer 2. Manages access to
media, fault recovery, and frame formatting. Runs at speeds
down to 10 Kb/s.