LTC2249 Linear Technology, LTC2249 Datasheet - Page 14

• Manufacturer Part Number: LTC2249
• Description: 80Msps Low Power 3V ADC
• Manufacturer: Linear Technology

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LTC2249
APPLICATIO S I FOR ATIO
The lower limit of the LTC2249 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2249 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2249 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OV
from the digital outputs.
14
LATCH
LTC2249
FROM
DATA
OE
PREDRIVER
LOGIC
DD
V
DD
voltages will also help reduce interference
Figure 12. Digital Output Buffer
U
U
V
DD
W
OV
DD
DD
and OGND, iso-
43Ω
2249 F12
U
OV
OGND
DD
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TYPICAL
DATA
OUTPUT
0.5V
TO V
0.1µF
DD
Data Format
Using the MODE pin, the LTC2249 parallel digital output
can be selected for offset binary or 2’s complement
format. Connecting MODE to GND or 1/3V
straight binary output format. Connecting MODE to
2/3V
An external resistor divider can be used to set the 1/3V
or 2/3V
the MODE pin.
Table 1. MODE Pin Function
MODE Pin
0
1/3V
2/3V
V
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OV
OV
the V
from GND up to 1V and must be less than OV
outputs will swing between OGND and OV
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data ac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration. The output Hi-Z state is intended for use during long
periods of inactivity.
DD
DD
DD
DD
DD
DD
can be powered with any voltage from 500mV up to
DD
of the part. OGND can be powered with any voltage
or V
logic values. Table 1 shows the logic states for
DD
2’s Complement
2’s Complement
DD
Output Format
Straight Binary
Straight Binary
selects 2’s complement output format.
should be tied to that same 1.8V supply.
Cycle Stablizer
Clock Duty
DD
, should be tied
Off
On
On
Off
DD
DD
.
DD
. The logic
selects
2249f
DD