LTC2249 Linear Technology, LTC2249 Datasheet - Page 8

• Manufacturer Part Number: LTC2249
• Description: 80Msps Low Power 3V ADC
• Manufacturer: Linear Technology

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PI FU CTIO S
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
outputs at high impedance. Connecting SHDN to V
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
results in sleep mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,
25, 26, 27): Digital Outputs. D13 is the MSB.
OGND (Pin 20): Output Driver Ground.
OV
Bypass to ground with 0.1µF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
LTC2249
FUNCTIONAL BLOCK DIAGRA
8
DD
U
U
(Pin 21): Positive Supply for the Output Drivers.
U
SENSE
2.2µF
A
A
V
IN
IN
CM
+
–
U
INPUT
DD
REFERENCE
S/H
SELECT
RANGE
1.5V
U
results in normal operation with the
REF
BUF
FIRST PIPELINED
ADC STAGE
DD
AMP
SECOND PIPELINED
DIFF
REF
and OE to V
ADC STAGE
Figure 1. Functional Block Diagram
1µF
REFH
REFH
W
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DD
0.1µF
2.2µF
and
REFL
DD
THIRD PIPELINED
REFL
ADC STAGE
1µF
INTERNAL CLOCK SIGNALS
straight binary output format and turns the clock duty
cycle stabilizer off. 1/3 V
format and turns the clock duty cycle stabilizer on. 2/3 V
selects 2’s complement output format and turns the clock
duty cycle stabilizer on. V
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to V
input range. V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±V
V
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
CM
CLOCK/DUTY
SENSE
CONTROL
CYCLE
CLK
(Pin 31): 1.5V Output and Input Common Mode Bias.
FOURTH PIPELINED
. ±1V is the largest valid input range.
ADC STAGE
CM
MODE
DD
selects the internal reference and a ±0.5V
CONTROL
selects the internal reference and a ±1V
LOGIC
SHDN
FIFTH PIPELINED
ADC STAGE
DD
OE
selects straight binary output
DD
selects 2’s complement
AND CORRECTION
SHIFT REGISTER
SIXTH PIPELINED
DRIVERS
OUTPUT
ADC STAGE
OGND
2249 F01
•
•
•
OF
D13
D0
OV
DD
2249f
DD