LTC2301 Linear Technology Corporation, LTC2301 Datasheet - Page 12

• Manufacturer Part Number: LTC2301
• Description: (LTC2301 / LTC2305) 12-Bit ADCs
• Manufacturer: Linear Technology Corporation

w w w . D a t a S h e e t 4 U . c o m
LTC2301/LTC2305
APPLICATIONS INFORMATION
Overview
The LTC2301/LTC2305 are low noise, 1-/2-channel, 12-bit
successive approximation register (SAR) A/D converters
with an I
LTC2305 both include a precision internal reference. The
LTC2305 includes a 2-channel analog input multiplexer
(MUX) while the LTC2301 includes an input MUX that allows
the polarity of the differential input to be selected. These
ADCs can operate in either unipolar or bipolar mode. Uni-
polar mode should be used for single-ended operation with
the LTC2305, since single-ended input signals are always
referenced to GND. A sleep mode option is also provided
to further reduce power during inactive periods.
The LTC2301/LTC2305 communicate through a 2-wire
I
by signaling a stop condition after the part has been
successfully addressed for a read/write operation. The
device will not acknowledge an external request until the
conversion is fi nished. After a conversion is fi nished, the
device is ready to accept a read/write request. Once the
LTC2301/LTC2305 is addressed for a read operation, the
device begins outputting the conversion result under the
control of the serial clock (SCL). There is no latency in the
conversion result. There are 12 bits of output data followed
by four trailing zeros. Data is updated on the falling edges
of SCL, allowing the user to reliably latch data on the ris-
ing edge of SCL. A write operation may follow the read
operation by using a repeat start or a stop condition may
be given to start a new conversion. By selecting a write
operation, these ADCs can be programmed by a 6-bit D
word. The D
various modes of operation.
During a conversion, the internal 12-bit capacitive charge-
redistribution DAC output is sequenced through a succes-
sive approximation algorithm by the SAR starting from the
most signifi cant bit (MSB) to the least signifi cant bit (LSB).
The sampled input is successively compared with binary
weighted charges supplied by the capacitive DAC using
a differential comparator. At the end of a conversion, the
DAC output balances the analog input. The SAR contents
12
2
C compatible serial interface. Conversions are initiated
2
C compatible serial interface. The LTC2301/
IN
word confi gures the MUX and programs
IN
(a 12-bit data word) that represent the sampled analog
input are loaded into 12 output latches that allow the data
to be shifted out via the I
Programming the LTC2301 and LTC2305
The software compatible LTC2301/LTC2305/LTC2309 fam-
ily features a 6-bit D
operation. Don’t care bits (X) are ignored. The SDA data
bits are loaded on the rising edge of SCL during a write
operation, with the S/D bit loaded on the fi rst rising edge
and the SLP bit on the sixth rising edge (see Figure 7b
in the I
LTC2305 is defi ned as follows:
For the LTC2301, the input word is defi ned as:
Analog Input Multiplexer
The analog input MUX is programmed by the S/D and
O/S bits of the D
bit of the D
list the MUX confi gurations for all combinations of the
confi guration bits. Figure 1a shows several possible MUX
confi gurations and Figure 1b shows how the MUX can be
reconfi gured from one conversion to the next.
Table 1. Channel Confi guration for the LTC2305
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
S/D O/S
X
S/D
2
0
0
1
1
C Interface section). The input data word for the
O/S
IN
word for the LTC2301. Table 1 and Table 2
X
X
IN
IN
O/S
word for the LTC2305 and the O/S
0
1
0
1
word to program various modes of
X
X
2
C interface.
UNI SLP
UNI SLP
CH0
+
–
+
CH1
–
+
+
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