LTC2301 Linear Technology Corporation, LTC2301 Datasheet - Page 16

• Manufacturer Part Number: LTC2301
• Description: (LTC2301 / LTC2305) 12-Bit ADCs
• Manufacturer: Linear Technology Corporation

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APPLICATIONS INFORMATION
LTC2301/LTC2305
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieve a typical conversion time (t
maximum conversion time of 1.6μs over the full operating
temperature range.
I
The LTC2301/LTC2305 communicate through an I
terface. The I
supporting multiple devices and multiple masters on a
single bus. The connected devices can only pull the serial
data line (SDA) low and can never drive it high. SDA is
required to be externally connected to the supply through
a pull-up resistor. When the data line is not being driven
low, it is high. Data on the I
rates up to 100kbits/s in the standard mode and up to
400kbits/s in the fast mode.
Each device on the I
address stored in the device and can only operate either
as a transmitter or receiver, depending on the function of
the device. A device can also be considered as a master
or a slave when performing data transfers. A master is
the device which initiates a data transfer on the bus and
generates the clock signals to permit the transfer. Devices
addressed by the master are considered slaves.
The LTC2301/LTC2305 can only be addressed as slaves.
Once addressed, they can receive confi guration bits (D
word) or transmit the last conversion result. The serial clock
line (SCL) is always an input to the LTC2301/LTC2305 and
the serial data line (SDA) is bidirectional. These devices
support the standard mode and the fast mode for data
transfer speeds up to 400kbits/s (see Timing Diagram
section for defi nition of the I
The Start and Stop Conditions
Referring to Figure 6, a Start (S) condition is generated
by transitioning SDA from high to low while SCL is high.
The bus is considered to be busy after the Start condition.
When the data transfer is fi nished, a Stop (P) condition
is generated by transitioning SDA from low to high while
SCL is high. The bus is free after a Stop condition is gen-
erated. Start and Stop conditions are always generated
by the master.
16
2
C Interface
2
C interface is a 2-wire open-drain interface
2
C bus is recognized by a unique
2
2
C bus can be transferred at
C timing).
CONV
) of 1.3μs and a
2
C in-
IN
When the bus is in use, it stays busy if a Repeated Start
(Sr) is generated instead of a Stop condition. The Repeated
Start timing is functionally identical to the Start and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the Start condition, the I
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit.
The master releases the SDA line during the ninth SCL
clock cycle. The slave device can issue an ACK by pulling
SDA low or issue a Not Acknowledge (NAK) by leaving
the SDA line high impedance (the external pull-up resistor
will hold the line high). Change of data only occurs while
the SCL line is low.
Data Format
After a Start condition, the master sends a 7-bit address
followed by a read/write (R/W) bit. The R/W bit is 1 for
a read request and 0 for a write request. If the 7-bit
address matches one of the LTC2301/LTC2305’s 9 pin-
selectable addresses (see Table 2), the ADC is selected.
When the ADC is addressed during a conversion, it will
not acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2301/LTC2305 issues an ACK by pulling the SDA
line low. The LTC2301/LTC2305 has two registers. The
12-bit wide output register contains the last conversion
result. The 6-bit wide input register confi gures the input
MUX and the operating mode of the ADC.
SDA
SCL
Figure 6. Timing Diagrams of Start and Stop Conditions
Start Condition
S
SDA
SCL
2
C bus is busy and data
Stop Condition
P
23015 F06
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