LTC3555 Linear Technology, LTC3555 Datasheet - Page 19

• Manufacturer Part Number: LTC3555
• Description: High Efficiency USB Power Manager + Triple Step-Down DC/DC
• Manufacturer: Linear Technology

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about the trip point. Grounding the NTC pin disables the
NTC charge pausing function.
Thermal Regulation
To optimize charging time, an internal thermal feedback
loop may automatically decrease the programmed charge
current. This will occur if the die temperature rises to
approximately 110°C. Thermal regulation protects the
LTC3555 from excessive temperature due to high power
operation or high ambient thermal conditions and allows
the user to push the limits of the power handling capability
with a given circuit board design without risk of damag-
ing the LTC3555 or external components. The benefi t
of the LTC3555 thermal regulation loop is that charge
current can be set according to actual conditions rather
than worst-case conditions with the assurance that the
battery charger will automatically reduce the current in
worst-case conditions.
I
The LTC3555 may receive commands from a host (mas-
ter) using the standard I
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 I
required on these lines. The LTC3555 is a receive-only
slave device. The I
scaled internally to the DV
nected to the same power supply as the microcontroller
generating the I
The I
pin. When DV
port is cleared and switching regulators 2 and 3 are set
to full scale.
Bus Speed
The I
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I
device. It also contains input fi lters designed to suppress
glitches should the bus become corrupted.
OPERATION
2
C Interface
2
2
C port is designed to be operated at speeds of up
C port has an undervoltage lockout on the DV
CC
2
is below approximately 1V, the I
C signals.
2
C control signals, SDA and SCL are
2
CC
C 2-wire interface. The Timing
supply. DV
2
C compliant master
2
CC
C accelerator, are
should be con-
2
C serial
CC
Start and Stop Conditions
A bus-master signals the beginning of a communication
to a slave device by transmitting a Start condition. A Start
condition is generated by transitioning SDA from high
to low while SCL is high. When the master has fi nished
communicating with the slave, it issues a Stop condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for communication with another I
device.
Byte Format
Each byte sent to the LTC3555 must be eight bits long
followed by an extra clock cycle for the Acknowledge bit
to be returned by the LTC3555. The data should be sent
to the LTC3555 most signifi cant bit (MSB) fi rst.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active low)
generated by the slave (LTC3555) lets the master know
that the latest byte of information was received. The
Acknowledge related clock pulse is generated by the
master. The master releases the SDA line (high) during
the Acknowledge clock cycle. The slave-receiver must pull
down the SDA line during the Acknowledge clock pulse
so that it remains a stable Low during the High period of
this clock pulse.
Slave Address
The LTC3555 responds to only one 7-bit address which
has been factory programmed to 0001001. The eighth
bit of the address byte (R/W) must be 0 for the LTC3555
to recognize the address since it is a write only device.
This effectively forces the address to be eight bits long
where the least signifi cant bit of the address is 0. If the
correct seven bit address is given but the R/W bit is 1,
the LTC3555 will not respond
Bus Write Operation
The master initiates communication with the LTC3555
with a Start condition and a 7-bit address followed by
the Write Bit R/W = 0. If the address matches that of the
LTC3555, the LTC3555 returns an Acknowledge. The master
LTC3555
19
3555f
2
C