LTC3835 Linear Technology, LTC3835 Datasheet - Page 11

• Manufacturer Part Number: LTC3835
• Description: Low IQ Synchronous Step-Down Controller
• Manufacturer: Linear Technology

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OPERATION
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping, or Continuous Conduction)
(PLLIN/MODE Pin)
The LTC3835 can be enabled to enter high effi ciency Burst
Mode operation, constant-frequency pulse-skipping mode,
or forced continuous conduction mode at low load currents.
To select Burst Mode operation, tie the PLLIN/MODE pin
to a DC voltage below 0.8V (e.g., SGND). To select forced
continuous operation, tie the PLLIN/MODE pin to INTV
select pulse-skipping mode, tie the PLLIN/MODE pin to a DC
voltage greater than 0.8V and less than INTV
When the LTC3835 is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-tenth of the maximum sense voltage even though the
voltage on the I
age inductor current is lower than the load current, the
error amplifi er EA will decrease the voltage on the I
When the I
signal goes high (enabling “sleep” mode) and both external
MOSFETs are turned off. The I
from the output of the EA and “parked” at 0.425V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3835 draws to
only 80μA. In sleep mode, the load current is supplied by
the output capacitor. As the output voltage decreases, the
EA’s output begins to rise. When the output voltage drops
enough, the I
EA, the sleep signal goes low, and the controller resumes
normal operation by turning on the top external MOSFET
on the next cycle of the internal oscillator.
When the LTC3835 is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (RI
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative, thus
operating in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by the
voltage on the I
mode, the effi ciency at light loads is lower than in Burst
Mode operation. However, continuous operation has the
TH
voltage drops below 0.4V, the internal sleep
TH
TH
TH
pin is reconnected to the output of the
pin, just as in normal operation. In this
pin indicates a lower value. If the aver-
(Refer to Functional Diagram)
CMP
) turns off the bottom external
TH
pin is then disconnected
CC
– 0.5V.
TH
CC
pin.
. To
advantages of lower output ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode or clocked by an external clock source to use the phase-
locked loop (see Frequency Selection and Phase-Locked
Loop section), the LTC3835 operates in PWM pulse-skipping
mode at light loads. In this mode, constant-frequency opera-
tion is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator I
force the external top MOSFET to stay off for the same number
of cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output ripple
as well as low audio noise and reduced RF interference as
compared to Burst Mode operation. It provides higher low
current effi ciency than forced continuous mode, but not
nearly as high as Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(PLLLPF and PLLIN/MODE Pins)
The selection of switching frequency is a tradeoff between
effi ciency and component size. Low frequency opera-
tion increases effi ciency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3835’s controllers can
be selected using the PLLLPF pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the PLLLPF pin can be fl oated, tied to INTV
or tied to SGND to select 400kHz, 530kHz, or 250kHz,
respectively.
A phase-locked loop (PLL) is available on the LTC3835
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. In this
case, a series R-C should be connected between the PLLLPF
pin and SGND to serve as the PLL’s loop fi lter. The LTC3835
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the external top MOSFET to the rising
edge of the synchronizing signal.
CMP
may remain tripped for several cycles and
LTC3835
11
3835fc
CC
,